improve System Control Module defines

This patch:

- prefaces the SCM register offsets with the appropriate platform string
  (e.g., OMAP2_ for 24xx/34xx-common registers) and updates code that uses
  these registers to use the correct name;

- adds some more register bit defines (e.g., OMAP2_DEVICETYPE_MASK) and
  cleans up code to use these common macros;

- fixes the offset of the CONTROL_STATUS register on 24xx that partially
  caused SRAM patcher problems (with thanks to Kyungmin Park
  <kmpark@infradead.org> for finding this problem)

- adds many more register offset defines for the 'GENERAL' section of the
  SCM.

Boot-tested on N800 and 2430SDP.  3430SDP is down at the moment, so
can't test there.  Incidentally, on N800, there is no vmlinux size
difference between unpatched and patched kernels.  Comments welcome.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 70c948c1c47a6fb7e82aeab8f4c239a82ac183e0..df434d71bcd1fe96de5032c4657d61cff78c3563 100644 (file)
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -272,7 +272,10 @@ static struct platform_device *h4_devices[] __initdata = {
 /* 2420 Sysboot setup (2430 is different) */
 static u32 get_sysboot_value(void)
 {
-       return (ctrl_read_reg(CONTROL_STATUS) & 0xFFF);
+       return (ctrl_read_reg(OMAP24XX_CONTROL_STATUS) &
+               (OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK |
+                OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK |
+                OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK));
 }
 
 /* FIXME: This function should be moved to some other file, gpmc.c? */

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 3b6e31520f664bf2a4d5822619eed71ebe1e6f42..ecb8a6ebb8efafd9c9cf71d3e08af927c70111dd 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -932,7 +932,7 @@ static struct clk mcbsp5_fck = {
        .init           = &omap2_init_clksel_parent,
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
-       .clksel_reg     = OMAP343X_CTRL_REGADDR(CONTROL_DEVCONF1),
+       .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
        .clksel         = mcbsp_15_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -944,7 +944,7 @@ static struct clk mcbsp1_fck = {
        .init           = &omap2_init_clksel_parent,
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
-       .clksel_reg     = OMAP343X_CTRL_REGADDR(CONTROL_DEVCONF0),
+       .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
        .clksel         = mcbsp_15_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2005,7 +2005,7 @@ static struct clk mcbsp2_fck = {
        .init           = &omap2_init_clksel_parent,
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
-       .clksel_reg     = OMAP343X_CTRL_REGADDR(CONTROL_DEVCONF0),
+       .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
        .clksel         = mcbsp_234_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2017,7 +2017,7 @@ static struct clk mcbsp3_fck = {
        .init           = &omap2_init_clksel_parent,
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
-       .clksel_reg     = OMAP343X_CTRL_REGADDR(CONTROL_DEVCONF1),
+       .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
        .clksel         = mcbsp_234_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2029,7 +2029,7 @@ static struct clk mcbsp4_fck = {
        .init           = &omap2_init_clksel_parent,
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
-       .clksel_reg     = OMAP343X_CTRL_REGADDR(CONTROL_DEVCONF1),
+       .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
        .clksel         = mcbsp_234_clksel,
        .flags          = CLOCK_IN_OMAP343X,

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 393b5932533847c6cd7c4575be1f4c846d76e489..1ac504bb7e72a4a93caf4fe48ceea0978047dbc3 100644 (file)
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -162,9 +162,23 @@ void __init omap2_check_revision(void)
        /* Embedding the ES revision info in type field */
        system_rev = omap_ids[j].type;
 
-       ctrl_status = ctrl_read_reg(CONTROL_STATUS);
-       system_rev |= (ctrl_status & 0x3f);
-       system_rev |= (ctrl_status & 0x700);
+       /* Add in the device type and sys_boot fields (see above) */
+       if (cpu_is_omap24xx()) {
+               i = OMAP24XX_CONTROL_STATUS;
+       } else if (cpu_is_omap343x()) {
+               i = OMAP343X_CONTROL_STATUS;
+       } else {
+               printk(KERN_ERR "id: unknown CPU type\n");
+               BUG();
+       }
+       ctrl_status = ctrl_read_reg(i);
+       system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK |
+                                     OMAP2_SYSBOOT_4_MASK |
+                                     OMAP2_SYSBOOT_3_MASK |
+                                     OMAP2_SYSBOOT_2_MASK |
+                                     OMAP2_SYSBOOT_1_MASK |
+                                     OMAP2_SYSBOOT_0_MASK));
+       system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK);
 
        pr_info("OMAP%04x", system_rev >> 16);
        if ((system_rev >> 8) & 0x0f)

diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index fe29760a1316cb66f041ab43e27172d05a0ddf0a..1e77957f5bf90455415d4a0c5e6921da8f18bee9 100644 (file)
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -414,8 +414,8 @@ static void omap2_enter_full_retention(void)
                          MPU_MOD, PM_PWSTCTRL);
 
        /* Workaround to kill USB */
-       l = ctrl_read_reg(CONTROL_DEVCONF0) | 0x00008000;
-       ctrl_write_reg(l, CONTROL_DEVCONF0);
+       l = ctrl_read_reg(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
+       ctrl_write_reg(l, OMAP2_CONTROL_DEVCONF0);
 
        omap2_gpio_prepare_for_retention();
 

diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index aa5c6cacefd62b602462399d9e5fb682a115bc92..427db48daa23a0210d1f8240f7249b5a9e595478 100644 (file)
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -280,9 +280,9 @@ static void __init omap_init_mmc(void)
                         * Module Input Clock selection
                         */
                        if (cpu_is_omap24xx()) {
-                               u32 v = ctrl_read_reg(CONTROL_DEVCONF0);
+                               u32 v = ctrl_read_reg(OMAP2_CONTROL_DEVCONF0);
                                v |= (1 << 24); /* not used in 243x */
-                               ctrl_write_reg(v, CONTROL_DEVCONF0);
+                               ctrl_write_reg(v, OMAP2_CONTROL_DEVCONF0);
                        }
                }
 #endif

diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index dd8dc0428a8f1254aeb4b3246302bcafc7c69236..afe81815fed80d8659556ebc718e4b25de9ff0f6 100644 (file)
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -49,7 +49,6 @@
 #define VA_READPERM0           IO_ADDRESS(0x68005050)
 #define VA_WRITEPERM0          IO_ADDRESS(0x68005058)
 #define GP_DEVICE              0x300
-#define TYPE_MASK              0x700
 
 #define ROUND_DOWN(value,boundary)     ((value) & (~((boundary)-1)))
 
@@ -94,7 +93,8 @@ static int is_sram_locked(void)
 
 #if defined(CONFIG_ARCH_OMAP242X)
        if (cpu_is_omap242x())
-               type = ctrl_read_reg(CONTROL_STATUS) & TYPE_MASK;
+               type = (ctrl_read_reg(OMAP24XX_CONTROL_STATUS) &
+                       OMAP2_DEVICETYPE_MASK);
 #endif
 
        if (type == GP_DEVICE) {

diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index ac00ebe6b53f31d762786bc786cfdd068506eed2..ec9034b4d3efe05a888dac47c467dd96e3986804 100644 (file)
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -116,36 +116,36 @@ static void omap2_usb_devconf_clear(u8 port, u32 mask)
 {
        u32 r;
 
-       r = ctrl_read_reg(CONTROL_DEVCONF0);
+       r = ctrl_read_reg(OMAP2_CONTROL_DEVCONF0);
        r &= ~USBTXWRMODEI(port, mask);
-       ctrl_write_reg(r, CONTROL_DEVCONF0);
+       ctrl_write_reg(r, OMAP2_CONTROL_DEVCONF0);
 }
 
 static void omap2_usb_devconf_set(u8 port, u32 mask)
 {
        u32 r;
 
-       r = ctrl_read_reg(CONTROL_DEVCONF0);
+       r = ctrl_read_reg(OMAP2_CONTROL_DEVCONF0);
        r |= USBTXWRMODEI(port, mask);
-       ctrl_write_reg(r, CONTROL_DEVCONF0);
+       ctrl_write_reg(r, OMAP2_CONTROL_DEVCONF0);
 }
 
 static void omap2_usb2_disable_5pinbitll(void)
 {
        u32 r;
 
-       r = ctrl_read_reg(CONTROL_DEVCONF0);
+       r = ctrl_read_reg(OMAP2_CONTROL_DEVCONF0);
        r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
-       ctrl_write_reg(r, CONTROL_DEVCONF0);
+       ctrl_write_reg(r, OMAP2_CONTROL_DEVCONF0);
 }
 
 static void omap2_usb2_enable_5pinunitll(void)
 {
        u32 r;
 
-       r = ctrl_read_reg(CONTROL_DEVCONF0);
+       r = ctrl_read_reg(OMAP2_CONTROL_DEVCONF0);
        r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
-       ctrl_write_reg(r, CONTROL_DEVCONF0);
+       ctrl_write_reg(r, OMAP2_CONTROL_DEVCONF0);
 }
 
 static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)

diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c
index 983337e8e0765df7d2e45ded9a685fb581545b04..2e8775e6eb6a2db6c10e429880c52d780215be09 100644 (file)
--- a/drivers/usb/gadget/omap_udc.c
+++ b/drivers/usb/gadget/omap_udc.c
@@ -52,6 +52,7 @@
 
 #include <asm/arch/dma.h>
 #include <asm/arch/usb.h>
+#include <asm/arch/control.h>
 
 #include "omap_udc.h"
 
@@ -2263,8 +2264,15 @@ static int proc_otg_show(struct seq_file *s)
 
        tmp = OTG_REV_REG;
        if (cpu_is_omap24xx()) {
+               /*
+                * REVISIT: Not clear how this works on OMAP2.  trans
+                * is ANDed to produce bits 7 and 8, which might make
+                * sense for USB_TRANSCEIVER_CTRL_REG on OMAP1,
+                * but with CONTROL_DEVCONF, these bits have something to
+                * do with the frame adjustment counter and McBSP2.
+                */
                ctrl_name = "control_devconf";
-               trans = CONTROL_DEVCONF_REG;
+               trans = ctrl_read_reg(CONTROL_DEVCONF0);
        } else {
                ctrl_name = "tranceiver_ctrl";
                trans = USB_TRANSCEIVER_CTRL_REG;

diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
index 5f42725df3cd583172a4575d51b435b78da94859..27509657b67d518b582f1b6eb733b9f99dd67bf7 100644 (file)
--- a/include/asm-arm/arch-omap/control.h
+++ b/include/asm-arm/arch-omap/control.h
@@ -22,37 +22,145 @@
 #define OMAP243X_CTRL_REGADDR(reg)     (void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + reg)
 #define OMAP343X_CTRL_REGADDR(reg)     (void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + reg)
 
+/*
+ * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
+ * OMAP24XX and OMAP34XX.
+ */
+
 /* Control submodule offsets */
 
-#define CONTROL_INTERFACE              0x000
-#define CONTROL_PADCONFS               0x030
-#define CONTROL_GENERAL                        0x270
-#define CONTROL_MEM_WKUP               0x600
-#define CONTROL_PADCONFS_WKUP          0xa00
-#define CONTROL_GENERAL_WKUP           0xa60
+#define OMAP2_CONTROL_INTERFACE                0x000
+#define OMAP2_CONTROL_PADCONFS         0x030
+#define OMAP2_CONTROL_GENERAL          0x270
+#define OMAP343X_CONTROL_MEM_WKUP      0x600
+#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
+#define OMAP343X_CONTROL_GENERAL_WKUP  0xa60
 
 /* Control register offsets - read/write with ctrl_{read,write}_reg() */
 
-#define CONTROL_SYSCONFIG              (CONTROL_INTERFACE + 0x10)
+#define OMAP2_CONTROL_SYSCONFIG                (OMAP2_CONTROL_INTERFACE + 0x10)
+
+/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
+#define OMAP2_CONTROL_DEVCONF0         (OMAP2_CONTROL_GENERAL + 0x0004)
+#define OMAP2_CONTROL_MSUSPENDMUX_0    (OMAP2_CONTROL_GENERAL + 0x0020)
+#define OMAP2_CONTROL_MSUSPENDMUX_1    (OMAP2_CONTROL_GENERAL + 0x0024)
+#define OMAP2_CONTROL_MSUSPENDMUX_2    (OMAP2_CONTROL_GENERAL + 0x0028)
+#define OMAP2_CONTROL_MSUSPENDMUX_3    (OMAP2_CONTROL_GENERAL + 0x002c)
+#define OMAP2_CONTROL_MSUSPENDMUX_4    (OMAP2_CONTROL_GENERAL + 0x0030)
+#define OMAP2_CONTROL_MSUSPENDMUX_5    (OMAP2_CONTROL_GENERAL + 0x0034)
+#define OMAP2_CONTROL_SEC_CTRL         (OMAP2_CONTROL_GENERAL + 0x0040)
+#define OMAP2_CONTROL_RPUB_KEY_H_0     (OMAP2_CONTROL_GENERAL + 0x0090)
+#define OMAP2_CONTROL_RPUB_KEY_H_1     (OMAP2_CONTROL_GENERAL + 0x0094)
+#define OMAP2_CONTROL_RPUB_KEY_H_2     (OMAP2_CONTROL_GENERAL + 0x0098)
+#define OMAP2_CONTROL_RPUB_KEY_H_3     (OMAP2_CONTROL_GENERAL + 0x009c)
+
+/* 242x-only CONTROL_GENERAL register offsets */
+#define OMAP242X_CONTROL_DEVCONF       OMAP2_CONTROL_DEVCONF0 /* match TRM */
+#define OMAP242X_CONTROL_OCM_RAM_PERM  (OMAP2_CONTROL_GENERAL + 0x0068)
 
-#define CONTROL_DEVCONF0               (CONTROL_GENERAL + 0x04)
-#define CONTROL_DEVCONF1               (CONTROL_GENERAL + 0x68) /* > 242x */
-#define CONTROL_STATUS                 (CONTROL_GENERAL + 0x80)
+/* 243x-only CONTROL_GENERAL register offsets */
+/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
+#define OMAP243X_CONTROL_DEVCONF1      (OMAP2_CONTROL_GENERAL + 0x0078)
+#define OMAP243X_CONTROL_CSIRXFE       (OMAP2_CONTROL_GENERAL + 0x007c)
+#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
+#define OMAP243X_CONTROL_IVA2_BOOTMOD  (OMAP2_CONTROL_GENERAL + 0x0194)
+#define OMAP243X_CONTROL_IVA2_GEMCFG   (OMAP2_CONTROL_GENERAL + 0x0198)
 
+/* 24xx-only CONTROL_GENERAL register offsets */
+#define OMAP24XX_CONTROL_DEBOBS                (OMAP2_CONTROL_GENERAL + 0x0000)
+#define OMAP24XX_CONTROL_EMU_SUPPORT   (OMAP2_CONTROL_GENERAL + 0x0008)
+#define OMAP24XX_CONTROL_SEC_TEST      (OMAP2_CONTROL_GENERAL + 0x0044)
+#define OMAP24XX_CONTROL_PSA_CTRL      (OMAP2_CONTROL_GENERAL + 0x0048)
+#define OMAP24XX_CONTROL_PSA_CMD       (OMAP2_CONTROL_GENERAL + 0x004c)
+#define OMAP24XX_CONTROL_PSA_VALUE     (OMAP2_CONTROL_GENERAL + 0x0050)
+#define OMAP24XX_CONTROL_SEC_EMU       (OMAP2_CONTROL_GENERAL + 0x0060)
+#define OMAP24XX_CONTROL_SEC_TAP       (OMAP2_CONTROL_GENERAL + 0x0064)
+#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD       (OMAP2_CONTROL_GENERAL + 0x006c)
+#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
+#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD  (OMAP2_CONTROL_GENERAL + 0x0074
+#define OMAP24XX_CONTROL_SEC_STATUS            (OMAP2_CONTROL_GENERAL + 0x0080)
+#define OMAP24XX_CONTROL_SEC_ERR_STATUS                (OMAP2_CONTROL_GENERAL + 0x0084)
+#define OMAP24XX_CONTROL_STATUS                        (OMAP2_CONTROL_GENERAL + 0x0088)
+#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS        (OMAP2_CONTROL_GENERAL + 0x008c)
+#define OMAP24XX_CONTROL_RAND_KEY_0    (OMAP2_CONTROL_GENERAL + 0x00a0)
+#define OMAP24XX_CONTROL_RAND_KEY_1    (OMAP2_CONTROL_GENERAL + 0x00a4)
+#define OMAP24XX_CONTROL_RAND_KEY_2    (OMAP2_CONTROL_GENERAL + 0x00a8)
+#define OMAP24XX_CONTROL_RAND_KEY_3    (OMAP2_CONTROL_GENERAL + 0x00ac)
+#define OMAP24XX_CONTROL_CUST_KEY_0    (OMAP2_CONTROL_GENERAL + 0x00b0)
+#define OMAP24XX_CONTROL_CUST_KEY_1    (OMAP2_CONTROL_GENERAL + 0x00b4)
+#define OMAP24XX_CONTROL_TEST_KEY_0    (OMAP2_CONTROL_GENERAL + 0x00c0)
+#define OMAP24XX_CONTROL_TEST_KEY_1    (OMAP2_CONTROL_GENERAL + 0x00c4)
+#define OMAP24XX_CONTROL_TEST_KEY_2    (OMAP2_CONTROL_GENERAL + 0x00c8)
+#define OMAP24XX_CONTROL_TEST_KEY_3    (OMAP2_CONTROL_GENERAL + 0x00cc)
+#define OMAP24XX_CONTROL_TEST_KEY_4    (OMAP2_CONTROL_GENERAL + 0x00d0)
+#define OMAP24XX_CONTROL_TEST_KEY_5    (OMAP2_CONTROL_GENERAL + 0x00d4)
+#define OMAP24XX_CONTROL_TEST_KEY_6    (OMAP2_CONTROL_GENERAL + 0x00d8)
+#define OMAP24XX_CONTROL_TEST_KEY_7    (OMAP2_CONTROL_GENERAL + 0x00dc)
+#define OMAP24XX_CONTROL_TEST_KEY_8    (OMAP2_CONTROL_GENERAL + 0x00e0)
+#define OMAP24XX_CONTROL_TEST_KEY_9    (OMAP2_CONTROL_GENERAL + 0x00e4)
+
+/* 34xx-only CONTROL_GENERAL register offsets */
+#define OMAP343X_CONTROL_PADCONF_OFF   (OMAP2_CONTROL_GENERAL + 0x0000)
+#define OMAP343X_CONTROL_MEM_DFTRW0    (OMAP2_CONTROL_GENERAL + 0x0008)
+#define OMAP343X_CONTROL_MEM_DFTRW1    (OMAP2_CONTROL_GENERAL + 0x000c)
+#define OMAP343X_CONTROL_DEVCONF1      (OMAP2_CONTROL_GENERAL + 0x0068)
+#define OMAP343X_CONTROL_CSIRXFE               (OMAP2_CONTROL_GENERAL + 0x006c)
+#define OMAP343X_CONTROL_SEC_STATUS            (OMAP2_CONTROL_GENERAL + 0x0070)
+#define OMAP343X_CONTROL_SEC_ERR_STATUS                (OMAP2_CONTROL_GENERAL + 0x0074)
+#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG  (OMAP2_CONTROL_GENERAL + 0x0078)
+#define OMAP343X_CONTROL_STATUS                        (OMAP2_CONTROL_GENERAL + 0x0080)
+#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS        (OMAP2_CONTROL_GENERAL + 0x0084)
+#define OMAP343X_CONTROL_RPUB_KEY_H_4  (OMAP2_CONTROL_GENERAL + 0x00a0)
+#define OMAP343X_CONTROL_RAND_KEY_0    (OMAP2_CONTROL_GENERAL + 0x00a8)
+#define OMAP343X_CONTROL_RAND_KEY_1    (OMAP2_CONTROL_GENERAL + 0x00ac)
+#define OMAP343X_CONTROL_RAND_KEY_2    (OMAP2_CONTROL_GENERAL + 0x00b0)
+#define OMAP343X_CONTROL_RAND_KEY_3    (OMAP2_CONTROL_GENERAL + 0x00b4)
+#define OMAP343X_CONTROL_TEST_KEY_0    (OMAP2_CONTROL_GENERAL + 0x00c8)
+#define OMAP343X_CONTROL_TEST_KEY_1    (OMAP2_CONTROL_GENERAL + 0x00cc)
+#define OMAP343X_CONTROL_TEST_KEY_2    (OMAP2_CONTROL_GENERAL + 0x00d0)
+#define OMAP343X_CONTROL_TEST_KEY_3    (OMAP2_CONTROL_GENERAL + 0x00d4)
+#define OMAP343X_CONTROL_TEST_KEY_4    (OMAP2_CONTROL_GENERAL + 0x00d8)
+#define OMAP343X_CONTROL_TEST_KEY_5    (OMAP2_CONTROL_GENERAL + 0x00dc)
+#define OMAP343X_CONTROL_TEST_KEY_6    (OMAP2_CONTROL_GENERAL + 0x00e0)
+#define OMAP343X_CONTROL_TEST_KEY_7    (OMAP2_CONTROL_GENERAL + 0x00e4)
+#define OMAP343X_CONTROL_TEST_KEY_8    (OMAP2_CONTROL_GENERAL + 0x00e8)
+#define OMAP343X_CONTROL_TEST_KEY_9    (OMAP2_CONTROL_GENERAL + 0x00ec)
+#define OMAP343X_CONTROL_TEST_KEY_10   (OMAP2_CONTROL_GENERAL + 0x00f0)
+#define OMAP343X_CONTROL_TEST_KEY_11   (OMAP2_CONTROL_GENERAL + 0x00f4)
+#define OMAP343X_CONTROL_TEST_KEY_12   (OMAP2_CONTROL_GENERAL + 0x00f8)
+#define OMAP343X_CONTROL_TEST_KEY_13   (OMAP2_CONTROL_GENERAL + 0x00fc)
+#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
+#define OMAP343X_CONTROL_IVA2_BOOTMOD  (OMAP2_CONTROL_GENERAL + 0x0194)
+
+/*
+ * REVISIT: This list of registers is not comprehensive - there are more
+ * that should be added.
+ */
 
 /*
  * Control module register bit defines - these should eventually go into
- * their own regbits file
+ * their own regbits file.  Some of these will be complicated, depending
+ * on the device type (general-purpose, emulator, test, secure, bad, other)
+ * and the security mode (secure, non-secure, don't care)
  */
 /* CONTROL_DEVCONF0 bits */
-#define OMAP2_MCBSP2_CLKS_MASK             (1 << 6)
-#define OMAP2_MCBSP1_CLKS_MASK             (1 << 2)
+#define OMAP24XX_USBSTANDBYCTRL                (1 << 15)
+#define OMAP2_MCBSP2_CLKS_MASK         (1 << 6)
+#define OMAP2_MCBSP1_CLKS_MASK         (1 << 2)
 
 /* CONTROL_DEVCONF1 bits */
-#define OMAP2_MCBSP5_CLKS_MASK             (1 << 4)
-#define OMAP2_MCBSP4_CLKS_MASK             (1 << 2)
-#define OMAP2_MCBSP3_CLKS_MASK             (1 << 0)
+#define OMAP2_MCBSP5_CLKS_MASK         (1 << 4) /* > 242x */
+#define OMAP2_MCBSP4_CLKS_MASK         (1 << 2) /* > 242x */
+#define OMAP2_MCBSP3_CLKS_MASK         (1 << 0) /* > 242x */
 
+/* CONTROL_STATUS bits */
+#define OMAP2_DEVICETYPE_MASK          (0x7 << 8)
+#define OMAP2_SYSBOOT_5_MASK           (1 << 5)
+#define OMAP2_SYSBOOT_4_MASK           (1 << 4)
+#define OMAP2_SYSBOOT_3_MASK           (1 << 3)
+#define OMAP2_SYSBOOT_2_MASK           (1 << 2)
+#define OMAP2_SYSBOOT_1_MASK           (1 << 1)
+#define OMAP2_SYSBOOT_0_MASK           (1 << 0)
 
 #endif /* __ASM_ARCH_CONTROL_H */