[ARM] OMAP2: Fix definition of SGX clock register bits

The GFX/SGX functional and interface clocks have different masks, for
some unknown reason, so split EN_SGX_SHIFT into one each for fclk and
iclk.

Correct according to the TRM and the far more important 'does this
actually work at all?' metric.

linux-omap source commit is de1121fdb899f762b9e717f44eaf3fae7c00cd3e.

Signed-off-by: Daniel Stone <daniel.stone@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 2c84717f95289b66fcb7112986e39eae8f10312a..6b39ad476336a14bdc995b72248c661db0a77ea8 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1293,7 +1293,7 @@ static struct clk sgx_fck = {
        .ops            = &clkops_omap2_dflt_wait,
        .init           = &omap2_init_clksel_parent,
        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
-       .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
+       .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
        .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
        .clksel         = sgx_clksel,
@@ -1307,7 +1307,7 @@ static struct clk sgx_ick = {
        .parent         = &l3_ick,
        .init           = &omap2_init_clk_clkdm,
        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
-       .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
+       .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
        .clkdm_name     = "sgx_clkdm",
        .recalc         = &followparent_recalc,
 };

diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index a46f93c399da44590e8d40ab26639ade44b8aeb7..f3c327bac1cbdaf5dd471b9c0a7f07de07d64c0a 100644 (file)
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -332,8 +332,12 @@
 #define OMAP3430ES1_CLKACTIVITY_GFX_MASK               (1 << 0)
 
 /* CM_FCLKEN_SGX */
-#define OMAP3430ES2_EN_SGX_SHIFT                       1
-#define OMAP3430ES2_EN_SGX_MASK                                (1 << 1)
+#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT         1
+#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK          (1 << 1)
+
+/* CM_ICLKEN_SGX */
+#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT         0
+#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK          (1 << 0)
 
 /* CM_CLKSEL_SGX */
 #define OMAP3430ES2_CLKSEL_SGX_SHIFT                   0