OMAP_DMA_CSDP_REG(lch) &= ~0x03;
OMAP_DMA_CSDP_REG(lch) |= data_type;
- if (cpu_class_is_omap1()) {
+ if (cpu_class_is_omap1()) {
OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
if (sync_mode == OMAP_DMA_SYNC_FRAME)
OMAP_DMA_CCR_REG(lch) |= 1 << 5;
if (cpu_is_omap24xx())
OMAP2_DMA_CSSA_REG(lch) = src_start;
-
+
OMAP_DMA_CSEI_REG(lch) = src_ei;
OMAP_DMA_CSFI_REG(lch) = src_fi;
}
}
if (cpu_is_omap24xx())
- OMAP2_DMA_CDSA_REG(lch) = dest_start;
+ OMAP2_DMA_CDSA_REG(lch) = dest_start;
OMAP_DMA_CDEI_REG(lch) = dst_ei;
OMAP_DMA_CDFI_REG(lch) = dst_fi;
if (cpu_is_omap24xx()) {
omap2_enable_irq_lch(free_ch);
-
+
omap_enable_channel_irq(free_ch);
/* Clear the CSR register and IRQ status register */
OMAP_DMA_CSR_REG(free_ch) = 0x0;
level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
OMAP_IRQ_BIT(INT_730_IH2_IRQ);
else if (cpu_is_omap1510())
- level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
+ level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
else if (cpu_is_omap16xx())
level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
#if defined(CONFIG_ARCH_OMAP730) && \
(defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
-#error "FIXME: OMAP730 doesn't support multiple-OMAP"
+#error "FIXME: OMAP730 doesn't support multiple-OMAP"
#elif defined(CONFIG_ARCH_OMAP730)
#define INT_IH2_IRQ INT_730_IH2_IRQ
#elif defined(CONFIG_ARCH_OMAP15XX)
},
-/*
+/*
* OMAP730 has a slightly different config for the pin mux.
- * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
+ * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
* not the FUNC_MUX_CTRL_x regs from hardware.h
- * - for pull-up/down, only has one enable bit which is is in the same register
+ * - for pull-up/down, only has one enable bit which is is in the same register
* as mux config
*/
#define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \
.mask = mode, \
.pull_val = pull_en, \
.pu_pd_val = pull_mode, \
-},
-
+},
+
#define PULL_DISABLED 0
#define PULL_ENABLED 1
if (!cpu_is_omap24xx())
omap1_arch_reset(mode);
else
- omap2_arch_reset(mode);
+ omap2_arch_reset(mode);
}
#endif
{
volatile u8 * uart = 0;
int shift = 2;
-
+
#ifdef CONFIG_MACH_OMAP_PALMTE
return;
#endif