ath9k: add udelay() for AR5416 on ath9k_hw_configpcipowersave()

We need the udelay() for all families, including AR5416.

Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index cfcaaf886d0304530428390d9b0c2116f9d05c5f..cad8e39c201eb6d3f3360b605ac0d100753363f6 100644 (file)
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -2666,7 +2666,6 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
                        REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
                                  INI_RA(&ah->iniPcieSerdes, i, 1));
                }
-               udelay(1000);
        } else if (AR_SREV_9280(ah) &&
                   (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
                REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
@@ -2690,7 +2689,6 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
                /* Load the new settings */
                REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 
-               udelay(1000);
        } else {
                REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
                REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
@@ -2714,6 +2712,8 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
                REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
        }
 
+       udelay(1000);
+
        /* set bit 19 to allow forcing of pcie core into L1 state */
        REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);