[ARM] xsc3: revert writethrough memory-type encoding change

Commit 40df2d1d "[ARM] Update Xscale and Xscale3 PTE mappings" was
fingered by git-bisect for a boot failure on iop13xx.  The change made
L_PTE_MT_WRITETHROUGH mappings L2-uncacheable.  Russell points out that
this mapping is used for the vector page.  Given the regression, and the
fact this page is used often, restore the old behaviour.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>

diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 04dc8b65401b4890b6ebc67eaac43f2c11d09169..8f6cf56c11c080fe9027777683bf1f8e39c2d882 100644 (file)
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -349,7 +349,7 @@ ENTRY(cpu_xsc3_switch_mm)
 cpu_xsc3_mt_table:
        .long   0x00                                            @ L_PTE_MT_UNCACHED
        .long   PTE_EXT_TEX(1)                                  @ L_PTE_MT_BUFFERABLE
-       .long   PTE_CACHEABLE                                   @ L_PTE_MT_WRITETHROUGH
+       .long   PTE_EXT_TEX(5) | PTE_CACHEABLE                  @ L_PTE_MT_WRITETHROUGH
        .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_WRITEBACK
        .long   PTE_EXT_TEX(1) | PTE_BUFFERABLE                 @ L_PTE_MT_DEV_SHARED
        .long   0x00                                            @ unused