[ARM] nommu: confirms the CR_V bit in nommu mode

In nommu mode, the exception vector location depends on the platforms.
Some of the implementations may have some special exception control
forwarding method in their ROM/flash and for some of them has its own
re-mapping mechanism by the h/w.

This patch introduces a special configuration CONFIG_CPU_HIGH_VECTOR which
turns on the CR_V bit in nommu mode. The CR_V bit is turned off by default.
This feature depends on CP15 and does not supported by ARM740.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2673fee3281cd0f45c433a6efe7ace34900041f1..ea7640af0f1e031248fc21768dba1c9f4a350fa7 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -95,7 +95,7 @@ config ARCH_MTD_XIP
 
 config VECTORS_BASE
        hex
-       default 0xffff0000 if MMU
+       default 0xffff0000 if MMU || CPU_HIGH_VECTOR
        default DRAM_BASE if REMAP_VECTORS_TO_RAM
        default 0x00000000
        help

diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 698a537915dd4ba5286f4909988934b8ad2d87f1..f359a189dcf2cda84f112dc0003e616cdd6434d4 100644 (file)
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -76,6 +76,11 @@ __after_proc_init:
 #endif
 #ifdef CONFIG_CPU_ICACHE_DISABLE
        bic     r0, r0, #CR_I
+#endif
+#ifdef CONFIG_CPU_HIGH_VECTOR
+       orr     r0, r0, #CR_V
+#else
+       bic     r0, r0, #CR_V
 #endif
        mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 #endif /* CONFIG_CPU_CP15 */

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 6c1bd424ea61bdf72e0b0b930eba49d2ce39b67e..c0bfb8212b7742abda15da17ffd47b09c3fe24e2 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -524,6 +524,18 @@ config CPU_BIG_ENDIAN
          port must properly enable any big-endian related features
          of your chipset/board/processor.
 
+config CPU_HIGH_VECTOR
+       depends !MMU && CPU_CP15 && !CPU_ARM740T
+       bool "Select the High exception vector"
+       default n
+       help
+         Say Y here to select high exception vector(0xFFFF0000~).
+         The exception vector can be vary depending on the platform
+         design in nommu mode. If your platform needs to select
+         high exception vector, say Y.
+         Otherwise or if you are unsure, say N, and the low exception
+         vector (0x00000000~) will be used.
+
 config CPU_ICACHE_DISABLE
        bool "Disable I-Cache (I-bit)"
        depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)