[ARM] 3352/1: DSB required for the completion of a TLB maintenance operation

Patch from Catalin Marinas

Chapter B2.7.3 in the latest ARM ARM (with v6 information) states that
the completion of a TLB maintenance operation is only guaranteed by
the execution of a DSB (Data Syncronization Barrier, formerly Data
Write Barrier or Drain Write Buffer).

Note that a DSB is only needed in the flush_tlb_kernel_* functions
since the completion is guaranteed by a mode change (i.e. switching
back to user mode) for the flush_tlb_user_* functions.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 15dc1a0dffbb6f2e048c837860bedf4b0c868779..9f80fa502f8fd975049fbe485ac87ed40898e822 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -78,7 +78,7 @@ menu "System Type"
 
 choice
        prompt "ARM system type"
-       default ARCH_RPC
+       default ARCH_VERSATILE
 
 config ARCH_CLPS7500
        bool "Cirrus-CL-PS7500FE"

diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S
index 6f76b89ef46eab52fa7dbcaa483003ba28dd6527..fd6adde39091ef28cadf0d4fa273d8376fbbe707 100644 (file)
--- a/arch/arm/mm/tlb-v6.S
+++ b/arch/arm/mm/tlb-v6.S
@@ -80,6 +80,7 @@ ENTRY(v6wbi_flush_kern_tlb_range)
        add     r0, r0, #PAGE_SZ
        cmp     r0, r1
        blo     1b
+       mcr     p15, 0, r2, c7, c10, 4          @ data synchronization barrier
        mov     pc, lr
 
        .section ".text.init", #alloc, #execinstr

diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 9387a5e1ffe007ef5ed62c4ad79308f651749118..0c2acc944a0a7bca9cb90ca6b7b5b15d4bb9025f 100644 (file)
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -340,6 +340,12 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
                asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
        if (tlb_flag(TLB_V6_I_PAGE))
                asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
+
+       /* The ARM ARM states that the completion of a TLB maintenance
+        * operation is only guaranteed by a DSB instruction
+        */
+       if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE))
+               asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
 }
 
 /*