[MIPS] SMTC: The MT ASE requires to initialize c0_pagemask and c0_wired.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 44f0a2c1180793f28423923f716182626d824b2b..a7a17eb9bfcde7ee4c71fd5bc7c2d73dd949091b 100644 (file)
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1384,6 +1384,13 @@ void __init per_cpu_trap_init(void)
                cpu_cache_init();
                tlb_init();
 #ifdef CONFIG_MIPS_MT_SMTC
+       } else if (!secondaryTC) {
+               /*
+                * First TC in non-boot VPE must do subset of tlb_init()
+                * for MMU countrol registers.
+                */
+               write_c0_pagemask(PM_DEFAULT_MASK);
+               write_c0_wired(0);
        }
 #endif /* CONFIG_MIPS_MT_SMTC */
 }