]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
[SCSI] stex: extend hard reset wait time
authorEd Lin <ed.lin@promise.com>
Thu, 10 May 2007 04:50:37 +0000 (20:50 -0800)
committerJames Bottomley <jejb@mulgrave.il.steeleye.com>
Wed, 16 May 2007 16:40:51 +0000 (12:40 -0400)
During hard bus reset of st_shasta controllers, 1 ms is not enough for
16-port controllers, although it's good for 8-port controllers.  Extend the
wait time to 100  ms to allow bus resets finish successfully.

Signed-off-by: Ed Lin <ed.lin@promise.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
drivers/scsi/stex.c

index 96dcbac9545e9fe81e0d6b4a61a7e971c8de9ac3..81dd3b740daf8d713a96b53dffe4fcec92082dcc 100644 (file)
@@ -1041,7 +1041,12 @@ static void stex_hard_reset(struct st_hba *hba)
        pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
        pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
        pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
-       msleep(1);
+
+       /*
+        * 1 ms may be enough for 8-port controllers. But 16-port controllers
+        * require more time to finish bus reset. Use 100 ms here for safety
+        */
+       msleep(100);
        pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
        pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);