void __init sdp2430_flash_init(void)
{
- unsigned long gpmc_base_add, gpmc_cs_base_add;
+ void __iomem *gpmc_base_add, *gpmc_cs_base_add;
unsigned char cs = 0;
- gpmc_base_add = OMAP243X_GPMC_VIRT;
+ gpmc_base_add = (__force void __iomem *)OMAP243X_GPMC_VIRT;
while (cs < GPMC_CS_NUM) {
int ret = 0;
/* Each GPMC set for a single CS is at offset 0x30 */
- gpmc_cs_base_add =
- (gpmc_base_add + GPMC_OFF_CONFIG1_0 + (cs*0x30));
+ gpmc_cs_base_add = (gpmc_base_add + GPMC_OFF_CONFIG1_0 +
+ (cs*0x30));
/* xloader/Uboot would have programmed the NAND/oneNAND
* base address for us This is a ugly hack. The proper
}
if (flash_type == NAND) {
- sdp_nand_data.cs = cs;
- sdp_nand_data.gpmc_cs_baseaddr = (void *) gpmc_cs_base_add;
- sdp_nand_data.gpmc_baseaddr = (void *) gpmc_base_add;
+ sdp_nand_data.cs = cs;
+ sdp_nand_data.gpmc_cs_baseaddr = gpmc_cs_base_add;
+ sdp_nand_data.gpmc_baseaddr = gpmc_base_add;
if (platform_device_register(&sdp_nand_device) < 0) {
printk(KERN_ERR "Unable to register NAND device\n");
- return;
- }
+ return;
+ }
}
if (flash_type == ONENAND) {
- sdp_onenand_data.cs = cs;
+ sdp_onenand_data.cs = cs;
- if (platform_device_register(&sdp_onenand_device) < 0) {
- printk(KERN_ERR "Unable to register OneNAND device\n");
- return;
- }
+ if (platform_device_register(&sdp_onenand_device) < 0) {
+ printk(KERN_ERR "Unable to register OneNAND device\n");
+ return;
+ }
}
}
static int clkout2_mux_disabled = 0;
static u32 saved_mux[2];
+#define MUX_EAC_IOP2V(x) (__force void __iomem *)io_p2v(x)
+
static void n800_enable_eac_mux(void)
{
if (!eac_mux_disabled)
return;
- __raw_writel(saved_mux[1], IO_ADDRESS(0x48000124));
+ __raw_writel(saved_mux[1], MUX_EAC_IOP2V(0x48000124));
eac_mux_disabled = 0;
}
WARN_ON(eac_mux_disabled);
return;
}
- saved_mux[1] = __raw_readl(IO_ADDRESS(0x48000124));
- __raw_writel(0x1f1f1f1f, IO_ADDRESS(0x48000124));
+ saved_mux[1] = __raw_readl(MUX_EAC_IOP2V(0x48000124));
+ __raw_writel(0x1f1f1f1f, MUX_EAC_IOP2V(0x48000124));
eac_mux_disabled = 1;
}
{
if (!clkout2_mux_disabled)
return;
- __raw_writel(saved_mux[0], IO_ADDRESS(0x480000e8));
+ __raw_writel(saved_mux[0], MUX_EAC_IOP2V(0x480000e8));
clkout2_mux_disabled = 0;
}
WARN_ON(clkout2_mux_disabled);
return;
}
- saved_mux[0] = __raw_readl(IO_ADDRESS(0x480000e8));
+ saved_mux[0] = __raw_readl(MUX_EAC_IOP2V(0x480000e8));
l = saved_mux[0] & ~0xff;
l |= 0x1f;
- __raw_writel(l, IO_ADDRESS(0x480000e8));
+ __raw_writel(l, MUX_EAC_IOP2V(0x480000e8));
clkout2_mux_disabled = 1;
}
#include <../drivers/cbus/retu.h>
#include <../drivers/media/video/tcm825x.h>
+#include "board-n800.h"
+
#if defined (CONFIG_VIDEO_TCM825X) || defined (CONFIG_VIDEO_TCM825X_MODULE)
#define OMAP24XX_CAMERA_JAM_HACK
void __init nokia_n800_map_io(void);
void __init nokia_n800_init_irq(void);
+extern const struct tcm825x_platform_data n800_tcm825x_platform_data;
+
#endif
*reg = (__force void __iomem *)tmp;
}
-void __init omap2_clk_rewrite_base(struct clk *clk)
+static void __init omap2_clk_rewrite_base(struct clk *clk)
{
omap2_clk_check_reg(clk->flags, &clk->clksel_reg);
omap2_clk_check_reg(clk->flags, &clk->enable_reg);
static inline unsigned int mbox_read_reg(unsigned int reg)
{
- return __raw_readl(mbox_base + reg);
+ return __raw_readl((void __iomem *)(mbox_base + reg));
}
static inline void mbox_write_reg(unsigned int val, unsigned int reg)
{
- __raw_writel(val, mbox_base + reg);
+ __raw_writel(val, (void __iomem *)(mbox_base + reg));
}
/* Mailbox H/W preparations */
#define OMAP34XX_MCBSP_PDATA_SZ 0
#endif
-int __init omap2_mcbsp_init(void)
+static int __init omap2_mcbsp_init(void)
{
int i;
static inline unsigned long
omap_mmu_read_reg(struct omap_mmu *mmu, unsigned long reg)
{
- return __raw_readl(mmu->base + reg);
+ return __raw_readl((void __iomem *)(mmu->base + reg));
}
static inline void omap_mmu_write_reg(struct omap_mmu *mmu,
unsigned long val, unsigned long reg)
{
- __raw_writel(val, mmu->base + reg);
+ __raw_writel(val, (void __iomem *)(mmu->base + reg));
}
#endif /* __MACH_OMAP2_MMU_H */
#endif
#ifdef CONFIG_ARCH_OMAP24XX
-int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
+static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
{
static DEFINE_SPINLOCK(mux_spin_lock);
unsigned long flags;
#include <asm/mach/time.h>
#include <asm/atomic.h>
+#include <asm/arch/pm.h>
#include "pm.h"
unsigned short enable_dyn_sleep;
extern void serial_console_sleep(int enable);
extern int omap2_pm_debug;
#else
-#define omap2_read_32k_sync_counter() 0;
-#define serial_console_sleep(enable) do; while(0)
-#define pm_init_serial_console() do; while(0)
-#define omap2_pm_dump(mode,resume,us) do; while(0)
-#define serial_console_fclk_mask(f1,f2) do; while(0)
-#define omap2_pm_debug 0
+#define omap2_read_32k_sync_counter() 0
+#define serial_console_sleep(enable) do {} while (0);
+#define pm_init_serial_console() do {} while (0);
+#define omap2_pm_dump(mode, resume, us) do {} while (0);
+#define serial_console_fclk_mask(f1, f2) do {} while (0);
+#define omap2_pm_debug 0
#endif /* CONFIG_PM_DEBUG */
#endif
void (*err_notify)(void);
};
+extern struct omap_mbox mbox_dsp_info;
+
int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg, void *);
void omap_mbox_init_seq(struct omap_mbox *);