[TG3]: Disable GPHY autopowerdown

New CPMU devices contend with the GPHY for power management.  The GPHY
autopowerdown feature is enabled by default in the PHY and thus needs to
be disabled after every PHY reset.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 25e57d8ddb513bf5cdd73d5edbf93afa55cad236..b5c4799003e05711767e083caa9b9e0d244dccb4 100644 (file)
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1117,6 +1117,12 @@ static int tg3_phy_reset(struct tg3 *tp)
                        udelay(40);
                        tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
                }
+
+               /* Disable GPHY autopowerdown. */
+               tg3_writephy(tp, MII_TG3_MISC_SHDW,
+                            MII_TG3_MISC_SHDW_WREN |
+                            MII_TG3_MISC_SHDW_APD_SEL |
+                            MII_TG3_MISC_SHDW_APD_WKTM_84MS);
        }
 
 out:

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index f715b35dfd5457811811bccadd634ce544c441bd..5b799ff2c4d6b9730a56a629d9380e3b66d198bc 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1715,6 +1715,12 @@
 #define MII_TG3_ISTAT                  0x1a /* IRQ status register */
 #define MII_TG3_IMASK                  0x1b /* IRQ mask register */
 
+#define MII_TG3_MISC_SHDW              0x1c
+#define MII_TG3_MISC_SHDW_WREN         0x8000
+#define MII_TG3_MISC_SHDW_APD_SEL      0x2800
+
+#define MII_TG3_MISC_SHDW_APD_WKTM_84MS        0x0001
+
 /* ISTAT/IMASK event bits */
 #define MII_TG3_INT_LINKCHG            0x0002
 #define MII_TG3_INT_SPEEDCHG           0x0004