static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
{
int ret = -EINVAL;
- u32 div_off, field_mask, field_val, reg_val, validrate;
- u32 new_div = 0;
+ u32 field_mask, field_val, reg_val, new_div = 0;
+ unsigned long validrate;
void __iomem *div_addr;
if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
if (clk == &dpll_ck)
return omap2_reprogram_dpll(clk, rate);
- /* Isolate control register */
- div_off = clk->rate_offset;
-
validrate = omap2_clksel_round_rate(clk, rate, &new_div);
if (validrate != rate)
return ret;
reg_val = cm_read_reg(div_addr);
reg_val &= ~field_mask;
- reg_val |= (field_val << div_off);
+ reg_val |= (field_val << mask_to_shift(field_mask));
cm_write_reg(reg_val, div_addr);
wmb();
clk->rate = clk->parent->rate / new_div;