]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
[ARM] omap: make sure virtual mmio addresses are __iomem pointer-like
authorRussell King <rmk@dyn-67.arm.linux.org.uk>
Thu, 4 Sep 2008 13:29:01 +0000 (14:29 +0100)
committerTony Lindgren <tony@atomide.com>
Thu, 4 Sep 2008 22:39:28 +0000 (15:39 -0700)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/plat-omap/include/mach/fpga.h
arch/arm/plat-omap/include/mach/hardware.h

index c92e4b42b2899cc0e6fdad376813815734cd5341..47543545a1cef8adae7959f08cec36834165259c 100644 (file)
@@ -34,9 +34,9 @@ extern void omap1510_fpga_init_irq(void);
  * ---------------------------------------------------------------------------
  */
 /* maps in the FPGA registers and the ETHR registers */
-#define H2P2_DBG_FPGA_BASE             0xE8000000      /* VA */
-#define H2P2_DBG_FPGA_SIZE             SZ_4K           /* SIZE */
-#define H2P2_DBG_FPGA_START            0x04000000      /* PA */
+#define H2P2_DBG_FPGA_BASE             ((void __iomem *)0xE8000000)    /* VA */
+#define H2P2_DBG_FPGA_SIZE             SZ_4K                           /* SIZE */
+#define H2P2_DBG_FPGA_START            0x04000000                      /* PA */
 
 #define H2P2_DBG_FPGA_ETHR_START       (H2P2_DBG_FPGA_START + 0x300)
 #define H2P2_DBG_FPGA_FPGA_REV         (H2P2_DBG_FPGA_BASE + 0x10)     /* FPGA Revision */
@@ -85,9 +85,9 @@ struct h2p2_dbg_fpga {
  *  OMAP-1510 FPGA
  * ---------------------------------------------------------------------------
  */
-#define OMAP1510_FPGA_BASE                     0xE8000000      /* Virtual */
-#define OMAP1510_FPGA_SIZE                     SZ_4K
-#define OMAP1510_FPGA_START                    0x08000000      /* Physical */
+#define OMAP1510_FPGA_BASE             ((void __iomem *)0xE8000000)    /* VA */
+#define OMAP1510_FPGA_SIZE             SZ_4K
+#define OMAP1510_FPGA_START            0x08000000                      /* PA */
 
 /* Revision */
 #define OMAP1510_FPGA_REV_LOW                  (OMAP1510_FPGA_BASE + 0x0)
index 438de80feea6db03747b6bace3e78a038fb55ef3..7dbb3b68f1c117015f94d7f1ac61407f14d8fadc 100644 (file)
@@ -89,7 +89,7 @@
 #define DPLL_CTL               (0xfffecf00)
 
 /* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
-#define DSP_CONFIG_REG_BASE     (0xe1008000)
+#define DSP_CONFIG_REG_BASE     ((void __iomem *)0xe1008000)
 #define DSP_CKCTL              (DSP_CONFIG_REG_BASE + 0x0)
 #define DSP_IDLECT1            (DSP_CONFIG_REG_BASE + 0x4)
 #define DSP_IDLECT2            (DSP_CONFIG_REG_BASE + 0x8)