static char *decode_ep0stage(u8 stage)
{
switch(stage) {
- case MGC_END0_STAGE_SETUP: return "idle";
- case MGC_END0_STAGE_TX: return "in";
- case MGC_END0_STAGE_RX: return "out";
- case MGC_END0_STAGE_ACKWAIT: return "wait";
- case MGC_END0_STAGE_STATUSIN: return "in/status";
- case MGC_END0_STAGE_STATUSOUT: return "out/status";
+ case MUSB_EP0_STAGE_SETUP: return "idle";
+ case MUSB_EP0_STAGE_TX: return "in";
+ case MUSB_EP0_STAGE_RX: return "out";
+ case MUSB_EP0_STAGE_ACKWAIT: return "wait";
+ case MUSB_EP0_STAGE_STATUSIN: return "in/status";
+ case MUSB_EP0_STAGE_STATUSOUT: return "out/status";
default: return "?";
}
}
*/
static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
{
- musb->ep0_state = MGC_END0_STAGE_SETUP;
+ musb->ep0_state = MUSB_EP0_STAGE_SETUP;
musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
}
req->actual += tmp;
tmp = MUSB_CSR0_P_SVDRXPKTRDY;
if (tmp < 64 || req->actual == req->length) {
- this->ep0_state = MGC_END0_STAGE_STATUSIN;
+ this->ep0_state = MUSB_EP0_STAGE_STATUSIN;
tmp |= MUSB_CSR0_P_DATAEND;
} else
req = NULL;
/* update the flags */
if (fifo_count < MUSB_MAX_END0_PACKET
|| request->actual == request->length) {
- musb->ep0_state = MGC_END0_STAGE_STATUSOUT;
+ musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
csr |= MUSB_CSR0_P_DATAEND;
} else
request = NULL;
if (req->wLength == 0) {
if (req->bRequestType & USB_DIR_IN)
musb->ackpend |= MUSB_CSR0_TXPKTRDY;
- musb->ep0_state = MGC_END0_STAGE_ACKWAIT;
+ musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
} else if (req->bRequestType & USB_DIR_IN) {
- musb->ep0_state = MGC_END0_STAGE_TX;
+ musb->ep0_state = MUSB_EP0_STAGE_TX;
musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
while ((musb_readw(regs, MUSB_CSR0)
& MUSB_CSR0_RXPKTRDY) != 0)
cpu_relax();
musb->ackpend = 0;
} else
- musb->ep0_state = MGC_END0_STAGE_RX;
+ musb->ep0_state = MUSB_EP0_STAGE_RX;
}
static int
musb_writew(regs, MUSB_CSR0,
csr & ~MUSB_CSR0_P_SENTSTALL);
retval = IRQ_HANDLED;
- musb->ep0_state = MGC_END0_STAGE_SETUP;
+ musb->ep0_state = MUSB_EP0_STAGE_SETUP;
csr = musb_readw(regs, MUSB_CSR0);
}
if (csr & MUSB_CSR0_P_SETUPEND) {
musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
retval = IRQ_HANDLED;
- musb->ep0_state = MGC_END0_STAGE_SETUP;
+ musb->ep0_state = MUSB_EP0_STAGE_SETUP;
csr = musb_readw(regs, MUSB_CSR0);
/* NOTE: request may need completion */
}
*/
switch (musb->ep0_state) {
- case MGC_END0_STAGE_TX:
+ case MUSB_EP0_STAGE_TX:
/* irq on clearing txpktrdy */
if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
ep0_txstate(musb);
}
break;
- case MGC_END0_STAGE_RX:
+ case MUSB_EP0_STAGE_RX:
/* irq on set rxpktrdy */
if (csr & MUSB_CSR0_RXPKTRDY) {
ep0_rxstate(musb);
}
break;
- case MGC_END0_STAGE_STATUSIN:
+ case MUSB_EP0_STAGE_STATUSIN:
/* end of sequence #2 (OUT/RX state) or #3 (no data) */
/* update address (if needed) only @ the end of the
}
/* FALLTHROUGH */
- case MGC_END0_STAGE_STATUSOUT:
+ case MUSB_EP0_STAGE_STATUSOUT:
/* end of sequence #1: write to host (TX state) */
{
struct usb_request *req;
musb_g_ep0_giveback(musb, req);
}
retval = IRQ_HANDLED;
- musb->ep0_state = MGC_END0_STAGE_SETUP;
+ musb->ep0_state = MUSB_EP0_STAGE_SETUP;
/* FALLTHROUGH */
- case MGC_END0_STAGE_SETUP:
+ case MUSB_EP0_STAGE_SETUP:
if (csr & MUSB_CSR0_RXPKTRDY) {
struct usb_ctrlrequest setup;
int handled = 0;
* device/endpoint feature set/clear operations)
* plus SET_CONFIGURATION and others we must
*/
- case MGC_END0_STAGE_ACKWAIT:
+ case MUSB_EP0_STAGE_ACKWAIT:
handled = service_zero_data_request(
musb, &setup);
if (handled > 0) {
musb->ackpend |= MUSB_CSR0_P_DATAEND;
musb->ep0_state =
- MGC_END0_STAGE_STATUSIN;
+ MUSB_EP0_STAGE_STATUSIN;
}
break;
* requests that we can't forward, GET_DESCRIPTOR
* and others that we must
*/
- case MGC_END0_STAGE_TX:
+ case MUSB_EP0_STAGE_TX:
handled = service_in_request(musb, &setup);
if (handled > 0) {
musb->ackpend = MUSB_CSR0_TXPKTRDY
| MUSB_CSR0_P_DATAEND;
musb->ep0_state =
- MGC_END0_STAGE_STATUSOUT;
+ MUSB_EP0_STAGE_STATUSOUT;
}
break;
/* sequence #2 (OUT from host), always forward */
- default: /* MGC_END0_STAGE_RX */
+ default: /* MUSB_EP0_STAGE_RX */
break;
}
stall:
DBG(3, "stall (%d)\n", handled);
musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
- musb->ep0_state = MGC_END0_STAGE_SETUP;
+ musb->ep0_state = MUSB_EP0_STAGE_SETUP;
finish:
musb_writew(regs, MUSB_CSR0,
musb->ackpend);
}
break;
- case MGC_END0_STAGE_ACKWAIT:
+ case MUSB_EP0_STAGE_ACKWAIT:
/* This should not happen. But happens with tusb6010 with
* g_file_storage and high speed. Do nothing.
*/
/* "can't happen" */
WARN_ON(1);
musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
- musb->ep0_state = MGC_END0_STAGE_SETUP;
+ musb->ep0_state = MUSB_EP0_STAGE_SETUP;
break;
}
}
switch (musb->ep0_state) {
- case MGC_END0_STAGE_RX: /* control-OUT data */
- case MGC_END0_STAGE_TX: /* control-IN data */
- case MGC_END0_STAGE_ACKWAIT: /* zero-length data */
+ case MUSB_EP0_STAGE_RX: /* control-OUT data */
+ case MUSB_EP0_STAGE_TX: /* control-IN data */
+ case MUSB_EP0_STAGE_ACKWAIT: /* zero-length data */
status = 0;
break;
default:
musb_ep_select(musb->mregs, 0);
/* sequence #1, IN ... start writing the data */
- if (musb->ep0_state == MGC_END0_STAGE_TX)
+ if (musb->ep0_state == MUSB_EP0_STAGE_TX)
ep0_txstate(musb);
/* sequence #3, no-data ... issue IN status */
- else if (musb->ep0_state == MGC_END0_STAGE_ACKWAIT) {
+ else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
if (req->request.length)
status = -EINVAL;
else {
- musb->ep0_state = MGC_END0_STAGE_STATUSIN;
+ musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
musb_writew(regs, MUSB_CSR0,
musb->ackpend | MUSB_CSR0_P_DATAEND);
musb->ackpend = 0;
}
switch (musb->ep0_state) {
- case MGC_END0_STAGE_TX: /* control-IN data */
- case MGC_END0_STAGE_ACKWAIT: /* STALL for zero-length data */
- case MGC_END0_STAGE_RX: /* control-OUT data */
+ case MUSB_EP0_STAGE_TX: /* control-IN data */
+ case MUSB_EP0_STAGE_ACKWAIT: /* STALL for zero-length data */
+ case MUSB_EP0_STAGE_RX: /* control-OUT data */
status = 0;
musb_ep_select(base, 0);
csr = musb_readw(regs, MUSB_CSR0);
csr |= MUSB_CSR0_P_SENDSTALL;
musb_writew(regs, MUSB_CSR0, csr);
- musb->ep0_state = MGC_END0_STAGE_SETUP;
+ musb->ep0_state = MUSB_EP0_STAGE_SETUP;
break;
default:
DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
/* control transfers always start with SETUP */
is_in = 0;
hw_ep->out_qh = qh;
- musb->ep0_stage = MGC_END0_START;
+ musb->ep0_stage = MUSB_EP0_START;
buf = urb->setup_packet;
len = 8;
break;
struct usb_ctrlrequest *request;
switch (musb->ep0_stage) {
- case MGC_END0_IN:
+ case MUSB_EP0_IN:
fifo_dest = urb->transfer_buffer + urb->actual_length;
fifo_count = min(len, ((u16) (urb->transfer_buffer_length
- urb->actual_length)));
urb->transfer_buffer_length)
more = TRUE;
break;
- case MGC_END0_START:
+ case MUSB_EP0_START:
request = (struct usb_ctrlrequest *) urb->setup_packet;
if (!request->wLength) {
break;
} else if (request->bRequestType & USB_DIR_IN) {
DBG(4, "start IN-DATA\n");
- musb->ep0_stage = MGC_END0_IN;
+ musb->ep0_stage = MUSB_EP0_IN;
more = TRUE;
break;
} else {
DBG(4, "start OUT-DATA\n");
- musb->ep0_stage = MGC_END0_OUT;
+ musb->ep0_stage = MUSB_EP0_OUT;
more = TRUE;
}
/* FALLTHROUGH */
- case MGC_END0_OUT:
+ case MUSB_EP0_OUT:
fifo_count = min(qh->maxpacket, ((u16)
(urb->transfer_buffer_length
- urb->actual_length)));
csr, qh, len, urb, musb->ep0_stage);
/* if we just did status stage, we are done */
- if (MGC_END0_STATUS == musb->ep0_stage) {
+ if (MUSB_EP0_STATUS == musb->ep0_stage) {
retval = IRQ_HANDLED;
complete = TRUE;
}
/* call common logic and prepare response */
if (musb_h_ep0_continue(musb, len, urb)) {
/* more packets required */
- csr = (MGC_END0_IN == musb->ep0_stage)
+ csr = (MUSB_EP0_IN == musb->ep0_stage)
? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
} else {
/* data transfer complete; perform status phase */
| MUSB_CSR0_TXPKTRDY;
/* flag status stage */
- musb->ep0_stage = MGC_END0_STATUS;
+ musb->ep0_stage = MUSB_EP0_STATUS;
DBG(5, "ep0 STATUS, csr %04x\n", csr);
musb_writew(epio, MUSB_CSR0, csr);
retval = IRQ_HANDLED;
} else
- musb->ep0_stage = MGC_END0_IDLE;
+ musb->ep0_stage = MUSB_EP0_IDLE;
/* call completion handler if done */
if (complete)
/* host side ep0 states */
enum musb_h_ep0_state {
- MGC_END0_IDLE,
- MGC_END0_START, /* expect ack of setup */
- MGC_END0_IN, /* expect IN DATA */
- MGC_END0_OUT, /* expect ack of OUT DATA */
- MGC_END0_STATUS, /* expect ack of STATUS */
+ MUSB_EP0_IDLE,
+ MUSB_EP0_START, /* expect ack of setup */
+ MUSB_EP0_IN, /* expect IN DATA */
+ MUSB_EP0_OUT, /* expect ack of OUT DATA */
+ MUSB_EP0_STATUS, /* expect ack of STATUS */
} __attribute__ ((packed));
/* peripheral side ep0 states */
enum musb_g_ep0_state {
- MGC_END0_STAGE_SETUP, /* idle, waiting for setup */
- MGC_END0_STAGE_TX, /* IN data */
- MGC_END0_STAGE_RX, /* OUT data */
- MGC_END0_STAGE_STATUSIN, /* (after OUT data) */
- MGC_END0_STAGE_STATUSOUT, /* (after IN data) */
- MGC_END0_STAGE_ACKWAIT, /* after zlp, before statusin */
+ MUSB_EP0_STAGE_SETUP, /* idle, waiting for setup */
+ MUSB_EP0_STAGE_TX, /* IN data */
+ MUSB_EP0_STAGE_RX, /* OUT data */
+ MUSB_EP0_STAGE_STATUSIN, /* (after OUT data) */
+ MUSB_EP0_STAGE_STATUSOUT, /* (after IN data) */
+ MUSB_EP0_STAGE_ACKWAIT, /* after zlp, before statusin */
} __attribute__ ((packed));
/* OTG protocol constants */