DAVINCI_USB_USBINT_MASK
| DAVINCI_USB_TXINT_MASK
| DAVINCI_USB_RXINT_MASK);
- musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, 0);
+ musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, 0);
musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
if (is_dma_capable() && !dma_off)
static void otg_timer(unsigned long _musb)
{
struct musb *musb = (void *)_musb;
- void *__iomem mregs = musb->pRegs;
+ void *__iomem mregs = musb->mregs;
u8 devctl;
unsigned long flags;
*/
if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
- void *__iomem mregs = musb->pRegs;
+ void *__iomem mregs = musb->mregs;
u8 devctl = musb_readb(mregs, MGC_O_HDRC_DEVCTL);
int err = musb->int_usb & MGC_M_INTR_VBUSERROR;
void *__iomem tibase = musb->ctrl_base;
u32 revision;
- musb->pRegs += DAVINCI_BASE_OFFSET;
+ musb->mregs += DAVINCI_BASE_OFFSET;
#if 0
/* REVISIT there's something odd about clocking, this
* didn't appear do the job ...
* long time to fall, especially on EVM with huge C133.
*/
do {
- devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
if (!(devctl & MGC_M_DEVCTL_VBUS))
break;
if ((devctl & MGC_M_DEVCTL_VBUS) != warn) {
struct musb *musb,
const struct usb_ctrlrequest *pControlRequest)
{
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
int handled = 1;
u8 bResult[2], bEnd = 0;
const u8 bRecip = pControlRequest->bRequestType & USB_RECIP_MASK;
*/
static inline void musb_try_b_hnp_enable(struct musb *musb)
{
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
u8 devctl;
DBG(1, "HNP: Setting HR\n");
__acquires(musb->Lock)
{
int handled = -EINVAL;
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
const u8 bRecip = pControlRequest->bRequestType & USB_RECIP_MASK;
/* the gadget driver handles everything except what we MUST handle */
{
u16 wCsrVal;
u16 wCount;
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
void __iomem *regs = musb->aLocalEnd[0].regs;
irqreturn_t retval = IRQ_NONE;
ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
req->request.length);
- MGC_SelectEnd(musb->pRegs, 0);
+ MGC_SelectEnd(musb->mregs, 0);
/* sequence #1, IN ... start writing the data */
if (musb->ep0_state == MGC_END0_STAGE_TX)
ep = to_musb_ep(e);
musb = ep->musb;
- base = musb->pRegs;
+ base = musb->mregs;
regs = musb->control_ep->regs;
spin_lock_irqsave(&musb->Lock, flags);
{
u16 wCsrVal;
struct usb_request *pRequest;
- u8 __iomem *pBase = musb->pRegs;
+ u8 __iomem *pBase = musb->mregs;
struct musb_ep *musb_ep = &musb->aLocalEnd[bEnd].ep_in;
void __iomem *epio = musb->aLocalEnd[bEnd].regs;
struct dma_channel *dma;
{
u16 wCsrVal;
struct usb_request *pRequest;
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
struct musb_ep *musb_ep = &musb->aLocalEnd[bEnd].ep_out;
void __iomem *epio = musb->aLocalEnd[bEnd].regs;
struct dma_channel *dma;
hw_ep = musb_ep->hw_ep;
regs = hw_ep->regs;
musb = musb_ep->musb;
- pBase = musb->pRegs;
+ pBase = musb->mregs;
bEnd = musb_ep->bEndNumber;
spin_lock_irqsave(&musb->Lock, flags);
epio = musb->aLocalEnd[bEnd].regs;
spin_lock_irqsave(&musb->Lock, flags);
- MGC_SelectEnd(musb->pRegs, bEnd);
+ MGC_SelectEnd(musb->mregs, bEnd);
/* zero the endpoint sizes */
if (musb_ep->is_in) {
- u16 wIntrTxE = musb_readw(musb->pRegs, MGC_O_HDRC_INTRTXE);
+ u16 wIntrTxE = musb_readw(musb->mregs, MGC_O_HDRC_INTRTXE);
wIntrTxE &= ~(1 << bEnd);
- musb_writew(musb->pRegs, MGC_O_HDRC_INTRTXE, wIntrTxE);
+ musb_writew(musb->mregs, MGC_O_HDRC_INTRTXE, wIntrTxE);
musb_writew(epio, MGC_O_HDRC_TXMAXP, 0);
} else {
- u16 wIntrRxE = musb_readw(musb->pRegs, MGC_O_HDRC_INTRRXE);
+ u16 wIntrRxE = musb_readw(musb->mregs, MGC_O_HDRC_INTRRXE);
wIntrRxE &= ~(1 << bEnd);
- musb_writew(musb->pRegs, MGC_O_HDRC_INTRRXE, wIntrRxE);
+ musb_writew(musb->mregs, MGC_O_HDRC_INTRRXE, wIntrRxE);
musb_writew(epio, MGC_O_HDRC_RXMAXP, 0);
}
req->bTx ? "TX/IN" : "RX/OUT",
&req->request, req->request.length, req->bEnd);
- MGC_SelectEnd(musb->pRegs, req->bEnd);
+ MGC_SelectEnd(musb->mregs, req->bEnd);
if (req->bTx)
txstate(musb, req);
else
else if (is_dma_capable() && musb_ep->dma) {
struct dma_controller *c = musb->pDmaController;
- MGC_SelectEnd(musb->pRegs, musb_ep->bEndNumber);
+ MGC_SelectEnd(musb->mregs, musb_ep->bEndNumber);
if (c->channel_abort)
status = c->channel_abort(musb_ep->dma);
else
if (!ep)
return -EINVAL;
- pBase = musb->pRegs;
+ pBase = musb->mregs;
spin_lock_irqsave(&musb->Lock, flags);
if (musb_ep->desc && !musb_ep->is_in) {
struct musb *musb = musb_ep->musb;
int bEnd = musb_ep->bEndNumber;
- void __iomem *mbase = musb->pRegs;
+ void __iomem *mbase = musb->mregs;
unsigned long flags;
spin_lock_irqsave(&musb->Lock, flags);
unsigned long flags;
u16 wCsr, wIntrTxE;
- mbase = musb->pRegs;
+ mbase = musb->mregs;
spin_lock_irqsave(&musb->Lock, flags);
MGC_SelectEnd(mbase, (u8) nEnd);
{
struct musb *musb = gadget_to_musb(gadget);
- return (int)musb_readw(musb->pRegs, MGC_O_HDRC_FRAME);
+ return (int)musb_readw(musb->mregs, MGC_O_HDRC_FRAME);
}
static int musb_gadget_wakeup(struct usb_gadget *gadget)
{
struct musb *musb = gadget_to_musb(gadget);
- void __iomem *mregs = musb->pRegs;
+ void __iomem *mregs = musb->mregs;
unsigned long flags;
int status = -EINVAL;
u8 power, devctl;
{
u8 power;
- power = musb_readb(musb->pRegs, MGC_O_HDRC_POWER);
+ power = musb_readb(musb->mregs, MGC_O_HDRC_POWER);
if (is_on)
power |= MGC_M_POWER_SOFTCONN;
else
DBG(3, "gadget %s D+ pullup %s\n",
musb->pGadgetDriver->function, is_on ? "on" : "off");
- musb_writeb(musb->pRegs, MGC_O_HDRC_POWER, power);
+ musb_writeb(musb->mregs, MGC_O_HDRC_POWER, power);
}
#if 0
for (i = 0, hw_ep = musb->aLocalEnd;
i < musb->bEndCount;
i++, hw_ep++) {
- MGC_SelectEnd(musb->pRegs, i);
+ MGC_SelectEnd(musb->mregs, i);
if (hw_ep->bIsSharedFifo /* || !bEnd */) {
nuke(&hw_ep->ep_in, -ESHUTDOWN);
} else {
{
u8 devctl;
- devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
DBG(3, "devctl %02x\n", devctl);
switch (musb->xceiv.state) {
/* called when VBUS drops below session threshold, and in other cases */
void musb_g_disconnect(struct musb *musb)
{
- void __iomem *mregs = musb->pRegs;
+ void __iomem *mregs = musb->mregs;
u8 devctl = musb_readb(mregs, MGC_O_HDRC_DEVCTL);
DBG(3, "devctl %02x\n", devctl);
__releases(musb->Lock)
__acquires(musb->Lock)
{
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
u8 devctl = musb_readb(pBase, MGC_O_HDRC_DEVCTL);
u8 power;
u16 wFrame;
u32 dwLength;
void *pBuffer;
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
struct urb *urb = next_urb(qh);
struct musb_hw_ep *hw_ep = qh->hw_ep;
unsigned nPipe = urb->pipe;
musb_writeb(ep->target_regs, MGC_O_HDRC_RXHUBPORT,
qh->h_port_reg);
} else
- musb_writeb(musb->pRegs, MGC_O_HDRC_FADDR, qh->addr_reg);
+ musb_writeb(musb->mregs, MGC_O_HDRC_FADDR, qh->addr_reg);
/* protocol/endpoint, interval/NAKlimit, i/o size */
musb_writeb(ep->regs, MGC_O_HDRC_RXTYPE, qh->type_reg);
struct dma_controller *pDmaController;
struct dma_channel *pDmaChannel;
u8 bDmaOk;
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
struct musb_hw_ep *hw_ep = musb->aLocalEnd + bEnd;
void __iomem *epio = hw_ep->regs;
struct musb_qh *qh;
struct urb *pUrb;
u16 wCsrVal, wCount;
int status = 0;
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
struct musb_hw_ep *hw_ep = musb->control_ep;
void __iomem *epio = hw_ep->regs;
struct musb_qh *qh = hw_ep->in_qh;
void __iomem *epio = hw_ep->regs;
struct musb_qh *qh = hw_ep->out_qh;
u32 status = 0;
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
struct dma_channel *dma;
pUrb = next_urb(qh);
void __iomem *epio = hw_ep->regs;
struct musb_qh *qh = hw_ep->in_qh;
size_t xfer_len;
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
int nPipe;
u16 wRxCsrVal, wVal;
u8 bIsochError = FALSE;
struct musb_hw_ep *ep = qh->hw_ep;
void __iomem *epio = ep->regs;
unsigned hw_end = ep->bLocalEnd;
- void __iomem *regs = ep->musb->pRegs;
+ void __iomem *regs = ep->musb->mregs;
u16 csr;
int status = 0;
{
struct musb *musb = hcd_to_musb(hcd);
- return musb_readw(musb->pRegs, MGC_O_HDRC_FRAME);
+ return musb_readw(musb->mregs, MGC_O_HDRC_FRAME);
}
static int musb_h_start(struct usb_hcd *hcd)
struct musb_hw_ep *hw_ep = &musb->aLocalEnd[bEnd];
do {
- MGC_SelectEnd(musb->pRegs, bEnd);
+ MGC_SelectEnd(musb->mregs, bEnd);
#ifdef CONFIG_USB_MUSB_HDRC_HCD
if (is_host_active(musb)) {
int dump_rx, dump_tx;
musb_readw(regs, MGC_O_HDRC_RXMAXP),
musb_readb(regs, MGC_O_HDRC_RXTYPE),
/* FIXME: assumes multipoint */
- musb_readb(musb->pRegs,
+ musb_readb(musb->mregs,
MGC_BUSCTL_OFFSET(bEnd,
MGC_O_HDRC_RXFUNCADDR)),
- musb_readb(musb->pRegs,
+ musb_readb(musb->mregs,
MGC_BUSCTL_OFFSET(bEnd,
MGC_O_HDRC_RXHUBADDR)),
- musb_readb(musb->pRegs,
+ musb_readb(musb->mregs,
MGC_BUSCTL_OFFSET(bEnd,
MGC_O_HDRC_RXHUBPORT))
);
musb_readw(regs, MGC_O_HDRC_TXMAXP),
musb_readb(regs, MGC_O_HDRC_TXTYPE),
/* FIXME: assumes multipoint */
- musb_readb(musb->pRegs,
+ musb_readb(musb->mregs,
MGC_BUSCTL_OFFSET(bEnd,
MGC_O_HDRC_TXFUNCADDR)),
- musb_readb(musb->pRegs,
+ musb_readb(musb->mregs,
MGC_BUSCTL_OFFSET(bEnd,
MGC_O_HDRC_TXHUBADDR)),
- musb_readb(musb->pRegs,
+ musb_readb(musb->mregs,
MGC_BUSCTL_OFFSET(bEnd,
MGC_O_HDRC_TXHUBPORT))
);
static int dump_header_stats(struct musb *musb, char *buffer)
{
int code, count = 0;
- const void __iomem *pBase = musb->pRegs;
+ const void __iomem *pBase = musb->mregs;
*buffer = 0;
count = sprintf(buffer, "Status: %sHDRC, Mode=%s "
char cmd;
u8 bReg;
struct musb *musb = (struct musb *)data;
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
/* MOD_INC_USE_COUNT; */
{ (_pthis)->bIsHost=FALSE; }
#define test_devctl_hst_mode(_x) \
- (musb_readb((_x)->pRegs, MGC_O_HDRC_DEVCTL)&MGC_M_DEVCTL_HM)
+ (musb_readb((_x)->mregs, MGC_O_HDRC_DEVCTL)&MGC_M_DEVCTL_HM)
#define MUSB_MODE(musb) ((musb)->bIsHost ? "Host" : "Peripheral")
struct device *controller;
void __iomem *ctrl_base;
- void __iomem *pRegs;
+ void __iomem *mregs;
#ifdef CONFIG_USB_TUSB6010
dma_addr_t async;
#define MGC_O_HDRC_INDEX 0x0E /* 8 bit */
#define MGC_O_HDRC_TESTMODE 0x0F /* 8 bit */
-/* Get offset for a given FIFO from musb->pRegs */
+/* Get offset for a given FIFO from musb->mregs */
#ifdef CONFIG_USB_TUSB6010
#define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20))
#else
* that must be ignored.
*/
- devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
if (is_on) {
musb->is_active = 1;
MUSB_DEV_MODE(musb);
}
- musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, devctl);
+ musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, devctl);
DBG(1, "VBUS %s, devctl %02x "
/* otg %3x conf %08x prcm %08x */ "\n",
otg_state_string(musb),
- musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL));
+ musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL));
}
static int omap_set_power(struct otg_transceiver *x, unsigned mA)
{
{
void __iomem *regs = musb->aLocalEnd[0].regs;
- MGC_SelectEnd(musb->pRegs, 0);
+ MGC_SelectEnd(musb->mregs, 0);
musb_write_fifo(musb->control_ep,
sizeof(musb_test_packet), musb_test_packet);
musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_TXPKTRDY);
void musb_hnp_stop(struct musb *musb)
{
struct usb_hcd *hcd = musb_to_hcd(musb);
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
u8 reg;
switch (musb->xceiv.state) {
{
irqreturn_t handled = IRQ_NONE;
#ifdef CONFIG_USB_MUSB_HDRC_HCD
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
#endif
DBG(3, "<== Power=%02x, DevCtl=%02x, bIntrUSB=0x%x\n", power, devctl,
* to support ISO transfers yet.
*/
if (bIntrUSB & MGC_M_INTR_SOF) {
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
struct musb_hw_ep *ep;
u8 bEnd;
u16 wFrame;
*/
void musb_start(struct musb *musb)
{
- void __iomem *regs = musb->pRegs;
+ void __iomem *regs = musb->mregs;
u8 devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
DBG(2, "<== devctl %02x\n", devctl);
static void musb_generic_disable(struct musb *musb)
{
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
u16 temp;
/* disable interrupts */
fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
const struct fifo_cfg *cfg, u16 offset)
{
- void __iomem *mbase = musb->pRegs;
+ void __iomem *mbase = musb->mregs;
int size = 0;
u16 maxpacket = cfg->maxpacket;
u16 c_off = offset >> 3;
{
u8 bEnd = 0, reg;
struct musb_hw_ep *hw_ep;
- void *pBase = musb->pRegs;
+ void *pBase = musb->mregs;
DBG(2, "<== static silicon ep config\n");
char *type;
u16 wRelease, wRelMajor, wRelMinor;
char aInfo[78], aRevision[32], aDate[12];
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
int status = 0;
int i;
spin_lock_irqsave(&musb->Lock, flags);
- musb->int_usb = musb_readb(musb->pRegs, MGC_O_HDRC_INTRUSB);
- musb->int_tx = musb_readw(musb->pRegs, MGC_O_HDRC_INTRTX);
- musb->int_rx = musb_readw(musb->pRegs, MGC_O_HDRC_INTRRX);
+ musb->int_usb = musb_readb(musb->mregs, MGC_O_HDRC_INTRUSB);
+ musb->int_tx = musb_readw(musb->mregs, MGC_O_HDRC_INTRTX);
+ musb->int_rx = musb_readw(musb->mregs, MGC_O_HDRC_INTRRX);
if (musb->int_usb || musb->int_tx || musb->int_rx)
retval = musb_interrupt(musb);
int ep_num;
u32 reg;
- devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
- power = musb_readb(musb->pRegs, MGC_O_HDRC_POWER);
+ devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
+ power = musb_readb(musb->mregs, MGC_O_HDRC_POWER);
DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
(devctl & MGC_M_DEVCTL_HM) ? "host" : "peripheral",
ep_num = 1;
while (reg) {
if (reg & 1) {
- // MGC_SelectEnd(musb->pRegs, ep_num);
+ // MGC_SelectEnd(musb->mregs, ep_num);
/* REVISIT just retval = ep->rx_irq(...) */
retval = IRQ_HANDLED;
if (devctl & MGC_M_DEVCTL_HM) {
ep_num = 1;
while (reg) {
if (reg & 1) {
- // MGC_SelectEnd(musb->pRegs, ep_num);
+ // MGC_SelectEnd(musb->mregs, ep_num);
/* REVISIT just retval |= ep->tx_irq(...) */
retval = IRQ_HANDLED;
if (devctl & MGC_M_DEVCTL_HM) {
void musb_dma_completion(struct musb *musb, u8 bLocalEnd, u8 bTransmit)
{
- u8 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
+ u8 devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
/* called with controller lock already held */
* VBUS high for a long time after power has been removed, can
* cause temporary false indications of a connection.
*/
- vbus = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
+ vbus = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
if (vbus & 0x10) {
/* REVISIT retest on real OTG hardware */
switch (musb->board_mode) {
#endif
- musb->pRegs = mbase;
+ musb->mregs = mbase;
musb->ctrl_base = mbase;
musb->nIrq = -ENODEV;
for (epnum = 0, ep = musb->aLocalEnd;
dma_controller_destroy(c);
}
- musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, 0);
+ musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, 0);
musb_platform_exit(musb);
- musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, 0);
+ musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, 0);
if (musb->clock) {
clk_disable(musb->clock);
*
* @pDevice: the controller (already clocked, etc)
* @nIrq: irq
- * @pRegs: virtual address of controller registers,
+ * @mregs: virtual address of controller registers,
* not yet corrected for platform-specific offsets
*/
static int __init
/* assume vbus is off */
- /* platform adjusts musb->pRegs and musb->isr if needed,
+ /* platform adjusts musb->mregs and musb->isr if needed,
* and activates clocks
*/
musb->isr = generic_interrupt;
if (use_dma && dev->dma_mask) {
struct dma_controller *c;
- c = dma_controller_create(musb, musb->pRegs);
+ c = dma_controller_create(musb, musb->mregs);
musb->pDmaController = c;
if (c)
(void) c->start(c->pPrivateData);
DBG(1, "%s mode, status %d, devctl %02x %c\n",
"HOST", status,
- musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL),
- (musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL)
+ musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL),
+ (musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL)
& MGC_M_DEVCTL_BDEVICE
? 'B' : 'A'));
DBG(1, "%s mode, status %d, dev%02x\n",
is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
status,
- musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL));
+ musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL));
}
prcm = musb_readl(base, TUSB_PRCM_MNGMT);
conf = musb_readl(base, TUSB_DEV_CONF);
- devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
if (is_on) {
musb->is_active = 1;
musb_writel(base, TUSB_PRCM_MNGMT, prcm);
musb_writel(base, TUSB_DEV_OTG_TIMER, timer);
musb_writel(base, TUSB_DEV_CONF, conf);
- musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, devctl);
+ musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, devctl);
DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
otg_state_string(musb),
- musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL),
+ musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL),
musb_readl(base, TUSB_DEV_OTG_STAT),
conf, prcm);
}
switch (musb->xceiv.state) {
case OTG_STATE_A_IDLE:
DBG(2, "Got SRP, turning on VBUS\n");
- devctl = musb_readb(musb->pRegs,
+ devctl = musb_readb(musb->mregs,
MGC_O_HDRC_DEVCTL);
devctl |= MGC_M_DEVCTL_SESSION;
- musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL,
+ musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL,
devctl);
musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
/* VBUS has probably been valid for a while now,
* but may well have bounced out of range a bit
*/
- devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
if ((devctl & MGC_M_DEVCTL_VBUS)
!= MGC_M_DEVCTL_VBUS) {
/* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
* FIFOs at 0x600, TUSB at 0x800
*/
- musb->pRegs += TUSB_BASE_OFFSET;
+ musb->mregs += TUSB_BASE_OFFSET;
ret = tusb_start(musb);
if (ret) {
struct musb *musb = chdat->musb;
struct musb_hw_ep *hw_ep = chdat->hw_ep;
void __iomem *ep_conf = hw_ep->conf;
- void __iomem *musb_base = musb->pRegs;
+ void __iomem *musb_base = musb->mregs;
unsigned long remaining, flags, pio;
int ch;
struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
struct musb *musb = chdat->musb;
struct musb_hw_ep *hw_ep = chdat->hw_ep;
- void __iomem *musb_base = musb->pRegs;
+ void __iomem *musb_base = musb->mregs;
void __iomem *ep_conf = hw_ep->conf;
dma_addr_t fifo = hw_ep->fifo_sync;
struct omap_dma_channel_params dma_params;
static void musb_port_suspend(struct musb *musb, u8 bSuspend)
{
u8 power;
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
if (!is_host_active(musb))
return;
static void musb_port_reset(struct musb *musb, u8 bReset)
{
u8 power;
- void __iomem *pBase = musb->pRegs;
+ void __iomem *pBase = musb->mregs;
#ifdef CONFIG_USB_MUSB_OTG
/* REVISIT this looks wrong for HNP */
&& time_after(jiffies, musb->rh_timer)) {
u8 power;
- power = musb_readb(musb->pRegs, MGC_O_HDRC_POWER);
+ power = musb_readb(musb->mregs, MGC_O_HDRC_POWER);
power &= ~MGC_M_POWER_RESUME;
DBG(4, "root port resume stopped, power %02x\n",
power);
- musb_writeb(musb->pRegs, MGC_O_HDRC_POWER, power);
+ musb_writeb(musb->mregs, MGC_O_HDRC_POWER, power);
/* ISSUE: DaVinci (RTL 1.300) disconnects after
* resume of high speed peripherals (but not full
temp = MGC_M_TEST_FORCE_HOST
| MGC_M_TEST_FORCE_HS;
- musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, MGC_M_DEVCTL_SESSION);
+ musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, MGC_M_DEVCTL_SESSION);
break;
case 6:
pr_debug("TEST_FIFO_ACCESS\n");
default:
goto error;
}
- musb_writeb(musb->pRegs, MGC_O_HDRC_TESTMODE, temp);
+ musb_writeb(musb->mregs, MGC_O_HDRC_TESTMODE, temp);
break;
default:
goto error;