[MIPS] Fix Cobalt PCI cache line sizes

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index b664df150a3ef80f6f78d64183946bbbf761971a..75a01e7648985c2cf20a84b5f76a4b13c03e6d43 100644 (file)
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -52,7 +52,7 @@ static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
        pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
        if (lt < 64)
                pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
-       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
 }
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
@@ -69,7 +69,7 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
         * host bridge.
         */
        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
-       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
 
        /*
         * The code described by the comment below has been removed