]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
ath5k: Correct usage of AR5K_CFG_ADHOC
authorSteve Brown <sbrown@cortland.com>
Tue, 23 Dec 2008 12:57:05 +0000 (07:57 -0500)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 12 Jan 2009 19:24:56 +0000 (14:24 -0500)
This corrects usage of AR5K_CFG_ADHOC introduced in
"ath5k: Update PCU code". Also,
the name of the indicator is changed to AR5K_CFG_IBSS to more
accurately reflect its function. This change restores
beaconing in AP and mesh modes.

Signed-off-by: Steve Brown <sbrown@cortland.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath5k/pcu.c
drivers/net/wireless/ath5k/reg.h

index 0cac05c6a9ce8dda1b1c50a5da26db3c187b9ecb..75eb9f43c7417980266d2eb652f7ac5a9ad70580 100644 (file)
@@ -65,7 +65,7 @@ int ath5k_hw_set_opmode(struct ath5k_hw *ah)
                if (ah->ah_version == AR5K_AR5210)
                        pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
                else
-                       AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_ADHOC);
+                       AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
                break;
 
        case NL80211_IFTYPE_AP:
@@ -75,7 +75,7 @@ int ath5k_hw_set_opmode(struct ath5k_hw *ah)
                if (ah->ah_version == AR5K_AR5210)
                        pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
                else
-                       AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_ADHOC);
+                       AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
                break;
 
        case NL80211_IFTYPE_STATION:
index 91aaeaf881995c583747feae712254a21e667872..9189ab13286cafde039c7201fec8ae17c456fde2 100644 (file)
@@ -73,7 +73,7 @@
 #define        AR5K_CFG_SWRD           0x00000004      /* Byte-swap RX descriptor */
 #define        AR5K_CFG_SWRB           0x00000008      /* Byte-swap RX buffer */
 #define        AR5K_CFG_SWRG           0x00000010      /* Byte-swap Register access */
-#define AR5K_CFG_ADHOC         0x00000020      /* AP/Adhoc indication [5211+] */
+#define AR5K_CFG_IBSS          0x00000020      /* 0-BSS, 1-IBSS [5211+] */
 #define AR5K_CFG_PHY_OK                0x00000100      /* [5211+] */
 #define AR5K_CFG_EEBS          0x00000200      /* EEPROM is busy */
 #define        AR5K_CFG_CLKGD          0x00000400      /* Clock gated (Disable dynamic clock) */