jme: GHC register control fix for new hardware

Due to the hardware design, except the first chip on the market,
other chips needs to setup the clock source for MAC processor
implicitly through Global Host Control Register(GHC).
(Strange design huh?)

10/100M uses the PCI-E as clock source, and 1G uses GPHY.

And I reordered the code a little, to make it easier to read.

Found-by: "Ethan" <ethanhsiao@jmicron.com>
Fixed-by: "akeemting" <akeem@jmicron.com>
Signed-off-by: "Guo-Fu Tseng" <cooldavid@cooldavid.org>
Acked-by: Jeff Garzik <jgarzik@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/jme.c b/drivers/net/jme.c
index c3873879003b80004125183c7d2951abb7f81ccc..e10d9f38662c6fce4e35c5e658bff0c8dbd98608 100644 (file)
--- a/drivers/net/jme.c
+++ b/drivers/net/jme.c
@@ -435,15 +435,18 @@ jme_check_link(struct net_device *netdev, int testonly)
                                        GHC_DPX);
                switch (phylink & PHY_LINK_SPEED_MASK) {
                case PHY_LINK_SPEED_10M:
-                       ghc |= GHC_SPEED_10M;
+                       ghc |= GHC_SPEED_10M |
+                               GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
                        strcat(linkmsg, "10 Mbps, ");
                        break;
                case PHY_LINK_SPEED_100M:
-                       ghc |= GHC_SPEED_100M;
+                       ghc |= GHC_SPEED_100M |
+                               GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
                        strcat(linkmsg, "100 Mbps, ");
                        break;
                case PHY_LINK_SPEED_1000M:
-                       ghc |= GHC_SPEED_1000M;
+                       ghc |= GHC_SPEED_1000M |
+                               GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
                        strcat(linkmsg, "1000 Mbps, ");
                        break;
                default:
@@ -463,14 +466,6 @@ jme_check_link(struct net_device *netdev, int testonly)
                                TXTRHD_TXREN |
                                ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
                }
-               strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
-                                       "Full-Duplex, " :
-                                       "Half-Duplex, ");
-
-               if (phylink & PHY_LINK_MDI_STAT)
-                       strcat(linkmsg, "MDI-X");
-               else
-                       strcat(linkmsg, "MDI");
 
                gpreg1 = GPREG1_DEFAULT;
                if (is_buggy250(jme->pdev->device, jme->chiprev)) {
@@ -492,11 +487,17 @@ jme_check_link(struct net_device *netdev, int testonly)
                                break;
                        }
                }
-               jwrite32(jme, JME_GPREG1, gpreg1);
 
-               jme->reg_ghc = ghc;
+               jwrite32(jme, JME_GPREG1, gpreg1);
                jwrite32(jme, JME_GHC, ghc);
+               jme->reg_ghc = ghc;
 
+               strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
+                                       "Full-Duplex, " :
+                                       "Half-Duplex, ");
+               strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
+                                       "MDI-X" :
+                                       "MDI");
                msg_link(jme, "Link is up at %s.\n", linkmsg);
                netif_carrier_on(netdev);
        } else {

diff --git a/drivers/net/jme.h b/drivers/net/jme.h
index f863aee6648b49b0db38d2cdc077640669a2a424..adaf3ddbf7835387bf6bca79f024d65919739ccb 100644 (file)
--- a/drivers/net/jme.h
+++ b/drivers/net/jme.h
@@ -815,16 +815,30 @@ static inline u32 smi_phy_addr(int x)
  * Global Host Control
  */
 enum jme_ghc_bit_mask {
-       GHC_SWRST       = 0x40000000,
-       GHC_DPX         = 0x00000040,
-       GHC_SPEED       = 0x00000030,
-       GHC_LINK_POLL   = 0x00000001,
+       GHC_SWRST               = 0x40000000,
+       GHC_DPX                 = 0x00000040,
+       GHC_SPEED               = 0x00000030,
+       GHC_LINK_POLL           = 0x00000001,
 };
 
 enum jme_ghc_speed_val {
-       GHC_SPEED_10M   = 0x00000010,
-       GHC_SPEED_100M  = 0x00000020,
-       GHC_SPEED_1000M = 0x00000030,
+       GHC_SPEED_10M           = 0x00000010,
+       GHC_SPEED_100M          = 0x00000020,
+       GHC_SPEED_1000M         = 0x00000030,
+};
+
+enum jme_ghc_to_clk {
+       GHC_TO_CLK_OFF          = 0x00000000,
+       GHC_TO_CLK_GPHY         = 0x00400000,
+       GHC_TO_CLK_PCIE         = 0x00800000,
+       GHC_TO_CLK_INVALID      = 0x00C00000,
+};
+
+enum jme_ghc_txmac_clk {
+       GHC_TXMAC_CLK_OFF       = 0x00000000,
+       GHC_TXMAC_CLK_GPHY      = 0x00100000,
+       GHC_TXMAC_CLK_PCIE      = 0x00200000,
+       GHC_TXMAC_CLK_INVALID   = 0x00300000,
 };
 
 /*