]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
[ARM] 4109/2: Add support for the RealView/EB MPCore revC platform
authorCatalin Marinas <catalin.marinas@arm.com>
Wed, 14 Feb 2007 18:20:28 +0000 (19:20 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Thu, 15 Feb 2007 14:56:32 +0000 (14:56 +0000)
The kernel originally supported revB only. This patch enables revC by
default and adds a config option for building the kernel for the revB
platform. Since the SCU base address was hard-coded in the proc-v6.S
file (and only valid for RealView/EB revB), this patch also adds a
more generic support for defining the SCU information.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mach-realview/Kconfig
arch/arm/mach-realview/realview_eb.c
arch/arm/mm/proc-v6.S
include/asm-arm/arch-realview/hardware.h
include/asm-arm/arch-realview/platform.h
include/asm-arm/arch-realview/scu.h [new file with mode: 0644]
include/asm-arm/hardware/arm_scu.h

index 17f5f4439fe756a966391732a83a02018ed94bd7..68bc6b226ec77bca2571651565ea414201355440 100644 (file)
@@ -16,4 +16,14 @@ config REALVIEW_MPCORE
          kernel built with this option enabled is not compatible with
          other tiles.
 
+config REALVIEW_MPCORE_REVB
+       bool "Support MPcore RevB tile"
+       depends on REALVIEW_MPCORE
+       default n
+       help
+         Enable support for the MPCore RevB tile on the Realview platform.
+         Since there are device address differences, a
+         kernel built with this option enabled is not compatible with
+         other tiles.
+
 endmenu
index 00139143dcc191ead307b12ec029791e4d1ed7ef..effe243454e04b613b55ab1b844daba9b643f29a 100644 (file)
@@ -152,9 +152,9 @@ static void __init gic_init_irq(void)
 #ifdef CONFIG_REALVIEW_MPCORE
        unsigned int pldctrl;
        writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
-       pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + 0xd8);
+       pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1);
        pldctrl |= 0x00800000;  /* New irq mode */
-       writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + 0xd8);
+       writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1);
        writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
 #endif
        gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29);
index 7b1843befb9c2deb693947e5cac5e1f5f8823d57..f27d9eb648032648c9b50d02b9251cbc93ecf99d 100644 (file)
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/elf.h>
-#include <asm/hardware/arm_scu.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 
+#ifdef CONFIG_SMP
+#include <asm/hardware/arm_scu.h>
+#endif
+
 #include "proc-macros.S"
 
 #define D_CACHE_LINE_SIZE      32
@@ -183,8 +186,7 @@ __v6_setup:
        /* Set up the SCU on core 0 only */
        mrc     p15, 0, r0, c0, c0, 5           @ CPU core number
        ands    r0, r0, #15
-       moveq   r0, #0x10000000 @ SCU_BASE
-       orreq   r0, r0, #0x00100000
+       ldreq   r0, =SCU_BASE
        ldreq   r5, [r0, #SCU_CTRL]
        orreq   r5, r5, #1
        streq   r5, [r0, #SCU_CTRL]
index 9ca76dc3a7af8ef39fbb6af750a3882ada9e5231..aa78fe087ab2a39cf9ed841aac5e97f42e318ab1 100644 (file)
@@ -26,7 +26,7 @@
 #include <asm/arch/platform.h>
 
 /* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x)          (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
+#define IO_ADDRESS(x)          ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000)
 #define __io_address(n)                __io(IO_ADDRESS(n))
 
 #endif
index bf52ca752a75335bbd83c86e14bd472ad92f31cd..87acd9c191e63a220a3984e2edf8285754f7cfd8 100644 (file)
 #define REALVIEW_GIC_CPU_BASE         0x10040000       /* Generic interrupt controller CPU interface */
 #define REALVIEW_GIC_DIST_BASE        0x10041000       /* Generic interrupt controller distributor */
 #else
+#ifdef CONFIG_REALVIEW_MPCORE_REVB
 #define REALVIEW_MPCORE_SCU_BASE       0x10100000      /*  SCU registers */
 #define REALVIEW_GIC_CPU_BASE          0x10100100      /* Generic interrupt controller CPU interface */
 #define REALVIEW_TWD_BASE              0x10100700
 #define REALVIEW_TWD_SIZE              0x00000100
 #define REALVIEW_GIC_DIST_BASE         0x10101000      /* Generic interrupt controller distributor */
+#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8             /*  Register offset for MPCore sysctl */
+#else
+#define REALVIEW_MPCORE_SCU_BASE      0x1F000000       /*  SCU registers */
+#define REALVIEW_GIC_CPU_BASE         0x1F000100       /* Generic interrupt controller CPU interface */
+#define REALVIEW_TWD_BASE             0x1F000700
+#define REALVIEW_TWD_SIZE             0x00000100
+#define REALVIEW_GIC_DIST_BASE        0x1F001000       /* Generic interrupt controller distributor */
+#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74             /*  Register offset for MPCore sysctl */
+#endif
 #define REALVIEW_GIC1_CPU_BASE        0x10040000       /* Generic interrupt controller CPU interface */
 #define REALVIEW_GIC1_DIST_BASE       0x10041000       /* Generic interrupt controller distributor */
 #endif
diff --git a/include/asm-arm/arch-realview/scu.h b/include/asm-arm/arch-realview/scu.h
new file mode 100644 (file)
index 0000000..cc29364
--- /dev/null
@@ -0,0 +1,8 @@
+#ifndef __ASMARM_ARCH_SCU_H
+#define __ASMARM_ARCH_SCU_H
+
+#include <asm/arch/platform.h>
+
+#define SCU_BASE       REALVIEW_MPCORE_SCU_BASE
+
+#endif
index 9903f60c84b713fdde431f61e33c87ba8f683be4..7d28eb5a17587ed0b4dbc3219d75e50fd52c5a4f 100644 (file)
@@ -1,6 +1,8 @@
 #ifndef ASMARM_HARDWARE_ARM_SCU_H
 #define ASMARM_HARDWARE_ARM_SCU_H
 
+#include <asm/arch/scu.h>
+
 /*
  * SCU registers
  */