x86: isolate PIC/PIT in/out calls

Rather than remove and/or mangle inb_p/outb_p we want to remove the use
of them from inappropriate places. For the PIC/PIT this may eventually
depend on 32/64bitism or similar so start by adding inb/outb_pit and
inb/outb_pic so that we can make them use any scheme we settle on without
disturbing the existing, correct (for ISA), port 0x80 usage. (eg we can
make inb_pit use udelay without messing up inb_p).

Floppy already does this for the fdc. That really only leaves the CMOS as
a core logic item to tackle, and bits of parallel port handling in the
chipset layers.

Signed-off-by: Alan Cox <alan@redhat.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index 955dd43b1676bddf16b09c0eefa295f5c7c0ac7a..d4438ef296d8a607f7a703a845040715a8335fd9 100644 (file)
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -1174,11 +1174,11 @@ static void reinit_timer(void)
 
        spin_lock_irqsave(&i8253_lock, flags);
        /* set the clock to HZ */
-       outb_p(0x34, PIT_MODE);         /* binary, mode 2, LSB/MSB, ch 0 */
+       outb_pit(0x34, PIT_MODE);               /* binary, mode 2, LSB/MSB, ch 0 */
        udelay(10);
-       outb_p(LATCH & 0xff, PIT_CH0);  /* LSB */
+       outb_pit(LATCH & 0xff, PIT_CH0);        /* LSB */
        udelay(10);
-       outb(LATCH >> 8, PIT_CH0);      /* MSB */
+       outb_pit(LATCH >> 8, PIT_CH0);  /* MSB */
        udelay(10);
        spin_unlock_irqrestore(&i8253_lock, flags);
 #endif

diff --git a/arch/x86/kernel/i8253.c b/arch/x86/kernel/i8253.c
index c76fef1ce355b77cebb34f81ccbc172aa5ab6759..ef62b07b2b488531255adf0a36824d4172028249 100644 (file)
--- a/arch/x86/kernel/i8253.c
+++ b/arch/x86/kernel/i8253.c
@@ -43,26 +43,26 @@ static void init_pit_timer(enum clock_event_mode mode,
        switch(mode) {
        case CLOCK_EVT_MODE_PERIODIC:
                /* binary, mode 2, LSB/MSB, ch 0 */
-               outb_p(0x34, PIT_MODE);
-               outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
-               outb(LATCH >> 8 , PIT_CH0);     /* MSB */
+               outb_pit(0x34, PIT_MODE);
+               outb_pit(LATCH & 0xff , PIT_CH0);       /* LSB */
+               outb_pit(LATCH >> 8 , PIT_CH0);         /* MSB */
                break;
 
        case CLOCK_EVT_MODE_SHUTDOWN:
        case CLOCK_EVT_MODE_UNUSED:
                if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
                    evt->mode == CLOCK_EVT_MODE_ONESHOT) {
-                       outb_p(0x30, PIT_MODE);
-                       outb_p(0, PIT_CH0);
-                       outb_p(0, PIT_CH0);
+                       outb_pit(0x30, PIT_MODE);
+                       outb_pit(0, PIT_CH0);
+                       outb_pit(0, PIT_CH0);
                }
                pit_disable_clocksource();
                break;
 
        case CLOCK_EVT_MODE_ONESHOT:
                /* One shot setup */
-               outb_p(0x38, PIT_MODE);
                pit_disable_clocksource();
+               outb_pit(0x38, PIT_MODE);
                break;
 
        case CLOCK_EVT_MODE_RESUME:
@@ -80,8 +80,8 @@ static void init_pit_timer(enum clock_event_mode mode,
 static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
 {
        spin_lock(&i8253_lock);
-       outb_p(delta & 0xff , PIT_CH0); /* LSB */
-       outb(delta >> 8 , PIT_CH0);     /* MSB */
+       outb_pit(delta & 0xff , PIT_CH0);       /* LSB */
+       outb_pit(delta >> 8 , PIT_CH0);         /* MSB */
        spin_unlock(&i8253_lock);
 
        return 0;
@@ -153,15 +153,15 @@ static cycle_t pit_read(void)
         * count), it cannot be newer.
         */
        jifs = jiffies;
-       outb_p(0x00, PIT_MODE); /* latch the count ASAP */
-       count = inb_p(PIT_CH0); /* read the latched count */
-       count |= inb_p(PIT_CH0) << 8;
+       outb_pit(0x00, PIT_MODE);       /* latch the count ASAP */
+       count = inb_pit(PIT_CH0);       /* read the latched count */
+       count |= inb_pit(PIT_CH0) << 8;
 
        /* VIA686a test code... reset the latch if count > max + 1 */
        if (count > LATCH) {
-               outb_p(0x34, PIT_MODE);
-               outb_p(LATCH & 0xff, PIT_CH0);
-               outb(LATCH >> 8, PIT_CH0);
+               outb_pit(0x34, PIT_MODE);
+               outb_pit(LATCH & 0xff, PIT_CH0);
+               outb_pit(LATCH >> 8, PIT_CH0);
                count = LATCH - 1;
        }
 

diff --git a/arch/x86/kernel/i8259_32.c b/arch/x86/kernel/i8259_32.c
index f201e7da1bbcea4a479ec2c98ae9357f4a44abae..2d25b77102fe19e964291713c94e1dd62a0b1466 100644 (file)
--- a/arch/x86/kernel/i8259_32.c
+++ b/arch/x86/kernel/i8259_32.c
@@ -289,20 +289,20 @@ void init_8259A(int auto_eoi)
        outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
 
        /*
-        * outb_p - this has to work on a wide range of PC hardware.
+        * outb_pic - this has to work on a wide range of PC hardware.
         */
-       outb_p(0x11, PIC_MASTER_CMD);   /* ICW1: select 8259A-1 init */
-       outb_p(0x20 + 0, PIC_MASTER_IMR);       /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
-       outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);   /* 8259A-1 (the master) has a slave on IR2 */
+       outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
+       outb_pic(0x20 + 0, PIC_MASTER_IMR);     /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
+       outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
        if (auto_eoi)   /* master does Auto EOI */
-               outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
+               outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
        else            /* master expects normal EOI */
-               outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
+               outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
 
-       outb_p(0x11, PIC_SLAVE_CMD);    /* ICW1: select 8259A-2 init */
-       outb_p(0x20 + 8, PIC_SLAVE_IMR);        /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
-       outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR);  /* 8259A-2 is a slave on master's IR2 */
-       outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
+       outb_pic(0x11, PIC_SLAVE_CMD);  /* ICW1: select 8259A-2 init */
+       outb_pic(0x20 + 8, PIC_SLAVE_IMR);      /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
+       outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);        /* 8259A-2 is a slave on master's IR2 */
+       outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
        if (auto_eoi)
                /*
                 * In AEOI mode we just have to mask the interrupt

diff --git a/arch/x86/kernel/i8259_64.c b/arch/x86/kernel/i8259_64.c
index 99c8406ae253913bec30606c4c69e32216bf8954..d3edb9f23f2c874b152d2cec34533e0d82022268 100644 (file)
--- a/arch/x86/kernel/i8259_64.c
+++ b/arch/x86/kernel/i8259_64.c
@@ -359,25 +359,25 @@ void init_8259A(int auto_eoi)
        outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
 
        /*
-        * outb_p - this has to work on a wide range of PC hardware.
+        * outb_pic - this has to work on a wide range of PC hardware.
         */
-       outb_p(0x11, PIC_MASTER_CMD);   /* ICW1: select 8259A-1 init */
+       outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
        /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */
-       outb_p(IRQ0_VECTOR, PIC_MASTER_IMR);
+       outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
        /* 8259A-1 (the master) has a slave on IR2 */
-       outb_p(0x04, PIC_MASTER_IMR);
+       outb_pic(0x04, PIC_MASTER_IMR);
        if (auto_eoi)   /* master does Auto EOI */
-               outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
+               outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
        else            /* master expects normal EOI */
-               outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
+               outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
 
-       outb_p(0x11, PIC_SLAVE_CMD);    /* ICW1: select 8259A-2 init */
+       outb_pic(0x11, PIC_SLAVE_CMD);  /* ICW1: select 8259A-2 init */
        /* ICW2: 8259A-2 IR0-7 mapped to 0x38-0x3f */
-       outb_p(IRQ8_VECTOR, PIC_SLAVE_IMR);
+       outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
        /* 8259A-2 is a slave on master's IR2 */
-       outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR);
+       outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
        /* (slave's support for AEOI in flat mode is to be investigated) */
-       outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
+       outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
 
        if (auto_eoi)
                /*

diff --git a/arch/x86/kernel/vmiclock_32.c b/arch/x86/kernel/vmiclock_32.c
index 57f9ef5a324cd99ae293b7ba677135b183f440b9..a2b030780aa9c1ce461384da18b20c287ac85b7c 100644 (file)
--- a/arch/x86/kernel/vmiclock_32.c
+++ b/arch/x86/kernel/vmiclock_32.c
@@ -237,7 +237,7 @@ static void __devinit vmi_time_init_clockevent(void)
 void __init vmi_time_init(void)
 {
        /* Disable PIT: BIOSes start PIT CH0 with 18.2hz peridic. */
-       outb_p(0x3a, PIT_MODE); /* binary, mode 5, LSB/MSB, ch 0 */
+       outb_pit(0x3a, PIT_MODE); /* binary, mode 5, LSB/MSB, ch 0 */
 
        vmi_time_init_clockevent();
        setup_irq(0, &vmi_clock_action);

diff --git a/include/asm-x86/i8253.h b/include/asm-x86/i8253.h
index 747548ec5d1ddce5fb1574b77b47d119f84e0754..b51c0487fc41d6aec43c7db474e80abd0330d50d 100644 (file)
--- a/include/asm-x86/i8253.h
+++ b/include/asm-x86/i8253.h
@@ -12,4 +12,7 @@ extern struct clock_event_device *global_clock_event;
 
 extern void setup_pit_timer(void);
 
+#define inb_pit                inb_p
+#define outb_pit       outb_p
+
 #endif /* __ASM_I8253_H__ */

diff --git a/include/asm-x86/i8259.h b/include/asm-x86/i8259.h
index cabcc6cf392358c697dccd4a3f1e3e64119460c8..67c319e0efc79f4975e1983e8a9f75e31465e434 100644 (file)
--- a/include/asm-x86/i8259.h
+++ b/include/asm-x86/i8259.h
@@ -29,4 +29,7 @@ extern void enable_8259A_irq(unsigned int irq);
 extern void disable_8259A_irq(unsigned int irq);
 extern unsigned int startup_8259A_irq(unsigned int irq);
 
+#define inb_pic                inb_p
+#define outb_pic       outb_p
+
 #endif /* __ASM_I8259_H__ */