This also fixes up a long-standing bug for this platform where the PIO
base was set to a register offset, rather than the actual PIO offset
itself.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
plat_irq_setup_pins(IRQ_MODE_IRQ);
}
-static void __iomem *sh03_ioport_map(unsigned long port, unsigned int size)
-{
- if (PXSEG(port))
- return (void __iomem *)port;
-
- return (void __iomem *)(port + PCI_IO_BASE);
-}
-
/* arch/sh/boards/sh03/rtc.c */
void sh03_time_init(void);
.mv_name = "Interface (CTP/PCI-SH03)",
.mv_setup = sh03_setup,
.mv_nr_irqs = 48,
- .mv_ioport_map = sh03_ioport_map,
.mv_init_irq = init_sh03_IRQ,
};
*/
int __init pcibios_init_platform(void)
{
- return 1;
+ __set_io_port_base(SH7751_PCI_IO_BASE);
+ return 1;
}
static struct resource sh7751_io_resource = {