[PATCH] x86: bug fix in P6 Machine check initialization

Make P6 MCA initialization code complaint with guidelines in IA-32 SDM
Vol3.  Bank 0 control register should not be set by OS and clear status
registers on all banks on reset.

This will prevent false MCE alarms on the systems that has some non-MCE
information left-over in MC0_STATUS on reboot.

Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

diff --git a/arch/i386/kernel/cpu/mcheck/p6.c b/arch/i386/kernel/cpu/mcheck/p6.c
index 3c035b8fa3d9bb9f0fd121826ce2eac01f69413d..979b18bc95c192aa4fe2740245d4923319124927 100644 (file)
--- a/arch/i386/kernel/cpu/mcheck/p6.c
+++ b/arch/i386/kernel/cpu/mcheck/p6.c
@@ -102,11 +102,16 @@ void __devinit intel_p6_mcheck_init(struct cpuinfo_x86 *c)
                wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
        nr_mce_banks = l & 0xff;
 
-       /* Don't enable bank 0 on intel P6 cores, it goes bang quickly. */
-       for (i=1; i<nr_mce_banks; i++) {
+       /*
+        * Following the example in IA-32 SDM Vol 3:
+        * - MC0_CTL should not be written
+        * - Status registers on all banks should be cleared on reset
+        */
+       for (i=1; i<nr_mce_banks; i++)
                wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
+
+       for (i=0; i<nr_mce_banks; i++)
                wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
-       }
 
        set_in_cr4 (X86_CR4_MCE);
        printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",