mem = request_mem_region(res->start, res->end - res->start + 1,
pdev->name);
- if (mem == NULL)
- return -EBUSY;
+ if (mem == NULL) {
+ ret = -EBUSY;
+ goto err_region;
+ }
dev_set_drvdata(&pdev->dev, mem);
- rng_base = (u32 __force __iomem *)io_p2v(res->start);
+ rng_base = ioremap(res->start, res->end - res->start + 1);
+ if (!rng_base) {
+ ret = -ENOMEM;
+ goto err_ioremap;
+ }
ret = hwrng_register(&omap_rng_ops);
- if (ret) {
- release_resource(mem);
- rng_base = NULL;
- return ret;
- }
+ if (ret)
+ goto err_register;
dev_info(&pdev->dev, "OMAP Random Number Generator ver. %02x\n",
omap_rng_read_reg(RNG_REV_REG));
rng_dev = pdev;
return 0;
+
+err_register:
+ iounmap(rng_base);
+ rng_base = NULL;
+err_ioremap:
+ release_resource(mem);
+err_region:
+ if (cpu_is_omap24xx()) {
+ clk_disable(rng_ick);
+ clk_put(rng_ick);
+ }
+ return ret;
}
static int __exit omap_rng_remove(struct platform_device *pdev)
omap_rng_write_reg(RNG_MASK_REG, 0x0);
+ iounmap(rng_base);
+
if (cpu_is_omap24xx()) {
clk_disable(rng_ick);
clk_put(rng_ick);
dev->speed = *speed;
dev->dev = &pdev->dev;
dev->irq = irq->start;
- dev->base = (void __iomem *) IO_ADDRESS(mem->start);
+ dev->base = ioremap(mem->start, mem->end - mem->start + 1);
+ if (!dev->base) {
+ r = -ENOMEM;
+ goto err_free_mem;
+ }
+
platform_set_drvdata(pdev, dev);
if ((r = omap_i2c_get_clocks(dev)) != 0)
- goto err_free_mem;
+ goto err_iounmap;
omap_i2c_unidle(dev);
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
omap_i2c_idle(dev);
omap_i2c_put_clocks(dev);
+err_iounmap:
+ iounmap(dev->base);
err_free_mem:
platform_set_drvdata(pdev, NULL);
kfree(dev);
i2c_del_adapter(&dev->adapter);
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
omap_i2c_put_clocks(dev);
+ iounmap(dev->base);
kfree(dev);
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(mem->start, (mem->end - mem->start) + 1);
host->irq = irq;
host->phys_base = host->mem_res->start;
- host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
+ host->virt_base = ioremap(res->start, res->end - res->start + 1);
+ if (!host->virt_base)
+ goto err_ioremap;
if (cpu_is_omap24xx()) {
host->iclk = clk_get(&pdev->dev, "mmc_ick");
clk_put(host->iclk);
}
err_free_mmc_host:
+ iounmap(host->virt_base);
+err_ioremap:
kfree(host);
err_free_mem_region:
release_mem_region(res->start, res->end - res->start + 1);
if (host->fclk && !IS_ERR(host->fclk))
clk_put(host->fclk);
+ iounmap(host->virt_base);
release_mem_region(pdev->resource[0].start,
pdev->resource[0].end - pdev->resource[0].start + 1);
}
mcspi->phys = r->start;
- mcspi->base = (void __iomem *) io_p2v(r->start);
+ mcspi->base = ioremap(r->start, r->end - r->start + 1);
+ if (!mcspi->base) {
+ dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
+ status = -ENOMEM;
+ goto err1aa;
+ }
INIT_WORK(&mcspi->work, omap2_mcspi_work);
err2:
clk_put(mcspi->ick);
err1a:
+ iounmap(mcspi->base);
+err1aa:
release_mem_region(r->start, (r->end - r->start) + 1);
err1:
spi_master_put(master);
struct omap2_mcspi *mcspi;
struct omap2_mcspi_dma *dma_channels;
struct resource *r;
+ void __iomem *base;
master = dev_get_drvdata(&pdev->dev);
mcspi = spi_master_get_devdata(master);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(r->start, (r->end - r->start) + 1);
+ base = mcspi->base;
spi_unregister_master(master);
+ iounmap(base);
kfree(dma_channels);
return 0;
* and irqs should show there too...
*/
#define UWIRE_BASE_PHYS 0xFFFB3000
-#define UWIRE_BASE ((void *__iomem)IO_ADDRESS(UWIRE_BASE_PHYS))
/* uWire Registers: */
#define UWIRE_IO_SIZE 0x20
};
/* REVISIT compile time constant for idx_shift? */
+/*
+ * Or, put it in a structure which is used throughout the driver;
+ * that avoids having to issue two loads for each bit of static data.
+ */
static unsigned int uwire_idx_shift;
+static void __iomem *uwire_base;
static inline void uwire_write_reg(int idx, u16 val)
{
- __raw_writew(val, UWIRE_BASE + (idx << uwire_idx_shift));
+ __raw_writew(val, uwire_base + (idx << uwire_idx_shift));
}
static inline u16 uwire_read_reg(int idx)
{
- return __raw_readw(UWIRE_BASE + (idx << uwire_idx_shift));
+ return __raw_readw(uwire_base + (idx << uwire_idx_shift));
}
static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
return -ENODEV;
uwire = spi_master_get_devdata(master);
+
+ uwire_base = ioremap(UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
+ if (!uwire_base) {
+ dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
+ spi_master_put(master);
+ return -ENOMEM;
+ }
+
dev_set_drvdata(&pdev->dev, uwire);
uwire->ck = clk_get(&pdev->dev, "armxor_ck");
uwire->bitbang.txrx_bufs = uwire_txrx;
status = spi_bitbang_start(&uwire->bitbang);
- if (status < 0)
+ if (status < 0) {
uwire_off(uwire);
+ iounmap(uwire_base);
+ }
return status;
}
status = spi_bitbang_stop(&uwire->bitbang);
uwire_off(uwire);
+ iounmap(uwire_base);
return status;
}
goto err1;
}
- hcd->regs = (void __iomem *) (int) IO_ADDRESS(hcd->rsrc_start);
+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+ if (!hcd->regs) {
+ dev_err(&pdev->dev, "can't ioremap OHCI HCD\n");
+ retval = -ENOMEM;
+ goto err2;
+ }
ohci = hcd_to_ohci(hcd);
ohci_hcd_init(ohci);
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
retval = -ENXIO;
- goto err2;
+ goto err3;
}
retval = usb_add_hcd(hcd, irq, IRQF_DISABLED);
if (retval)
- goto err2;
+ goto err3;
host_initialized = 1;
omap_ohci_clock_power(0);
return 0;
+err3:
+ iounmap(hcd->regs);
err2:
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
err1:
}
if (machine_is_omap_osk())
omap_free_gpio(9);
+ iounmap(hcd->regs);
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
usb_put_hcd(hcd);
clk_put(usb_dc_ck);
};
static struct {
- u32 base;
+ void __iomem *base;
struct omapfb_mem_desc mem_desc;
struct resmap *res_map[DISPC_MEMTYPE_NUM];
memset(&dispc, 0, sizeof(dispc));
- dispc.base = io_p2v(DISPC_BASE);
+ dispc.base = ioremap(DISPC_BASE, SZ_1K);
+ if (!dispc.base) {
+ dev_err(fbdev->dev, "can't ioremap DISPC\n");
+ return -ENOMEM;
+ }
+
dispc.fbdev = fbdev;
dispc.ext_mode = ext_mode;
init_completion(&dispc.frame_done);
if ((r = get_dss_clocks()) < 0)
- return r;
+ goto fail0;
enable_lcd_clocks(1);
fail1:
enable_lcd_clocks(0);
put_dss_clocks();
-
+fail0:
+ iounmap(dispc.base);
return r;
}
free_palette_ram();
free_irq(INT_24XX_DSS_IRQ, dispc.fbdev);
put_dss_clocks();
+ iounmap(dispc.base);
}
const struct lcd_ctrl omap2_int_ctrl = {
#define DISPC_CONTROL 0x0040
static struct {
- u32 base;
+ void __iomem *base;
void (*lcdc_callback)(void *data);
void *lcdc_callback_data;
unsigned long l4_khz;
int r;
rfbi.fbdev = fbdev;
- rfbi.base = io_p2v(RFBI_BASE);
+ rfbi.base = ioremap(RFBI_BASE, SZ_1K);
+ if (!rfbi.base) {
+ dev_err(fbdev->dev, "can't ioremap RFBI\n");
+ return -ENOMEM;
+ }
if ((r = rfbi_get_clocks()) < 0)
return r;
{
omap_dispc_free_irq();
rfbi_put_clocks();
+ iounmap(rfbi.base);
}
const struct lcd_ctrl_extif omap2_ext_if = {
struct clk *dpll1out_ck;
int r;
- sossi.base = (void __iomem *)IO_ADDRESS(OMAP_SOSSI_BASE);
+ sossi.base = ioremap(OMAP_SOSSI_BASE, SZ_1K);
+ if (!sossi.base) {
+ dev_err(fbdev->dev, "can't ioremap SoSSI\n");
+ return -ENOMEM;
+ }
+
sossi.fbdev = fbdev;
spin_lock_init(&sossi.lock);
{
omap_lcdc_free_dma_callback();
clk_put(sossi.fck);
+ iounmap(sossi.base);
}
struct lcd_ctrl_extif omap1_ext_if = {