musb_readl(c->stateRam, 4 * 4), /* flags */
musb_readl(c->stateRam, 5 * 4), /* len */
- // dummy/unused word 6
+ /* dummy/unused word 6 */
musb_readl(c->stateRam, 7 * 4) /* completion */
);
}
WARN("%cX DMA%d not cleaned up after abort!\n",
otgChannel->transmit ? 'T' : 'R',
otgChannel->chNo);
- //WARN_ON(1);
+ /* WARN_ON(1); */
break;
case MUSB_DMA_STATUS_BUSY:
WARN("program active channel? %cX DMA%d\n",
otgChannel->transmit ? 'T' : 'R',
otgChannel->chNo);
- //WARN_ON(1);
+ /* WARN_ON(1); */
break;
case MUSB_DMA_STATUS_UNKNOWN:
DBG(1, "%cX DMA%d not allocated!\n",
*
* REVISIT have observed bit 18 set; huh??
*/
-// if ((bdPtr->hOptions & CPPI_EOQ_MASK))
+ /* if ((bdPtr->hOptions & CPPI_EOQ_MASK)) */
txState->completionPtr = bdPtr->dma;
/* stop scanning on end-of-segment */
/* on end of segment, maybe go to next one */
if (bReqComplete) {
- //cppi_dump_tx(4, txChannel, "/complete");
+ /* cppi_dump_tx(4, txChannel, "/complete"); */
/* transfer more, or report completion */
if (txChannel->currOffset
musb_writel(regBase, DAVINCI_TXCPPI_INTCLR_REG,
(1 << otgCh->chNo));
- // REVISIT put timeouts on these controller handshakes
+ /* REVISIT put timeouts on these controller handshakes */
cppi_dump_tx(6, otgCh, " (teardown)");
/* CPPI data structure definitions */
-#define CPPI_DESCRIPTOR_ALIGN 16 // bytes; 5-dec docs say 4-byte align
+#define CPPI_DESCRIPTOR_ALIGN 16 /* bytes; 5-dec docs say 4-byte align */
struct cppi_descriptor {
/* Hardware Overlay */
s = "<AValid"; break;
case 2 << MUSB_DEVCTL_VBUS_SHIFT:
s = "<VBusValid"; break;
- //case 3 << MUSB_DEVCTL_VBUS_SHIFT:
+ /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
default:
s = "VALID"; break;
}; s; }),
#ifdef CONFIG_USB_MUSB_OTG
/* flush endpoints when transitioning from Device Mode */
if (is_peripheral_active(musb)) {
- // REVISIT HNP; just force disconnect
+ /* REVISIT HNP; just force disconnect */
}
musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
for (epnum = 1; (epnum < musb->nr_endpoints)
&& (musb->epmask >= (1 << epnum));
epnum++, ep++) {
- // FIXME handle framecounter wraps (12 bits)
- // eliminate duplicated StartUrb logic
+ /*
+ * FIXME handle framecounter wraps (12 bits)
+ * eliminate duplicated StartUrb logic
+ */
if (ep->dwWaitFrame >= frame) {
ep->dwWaitFrame = 0;
printk("SOF --> periodic TX%s on %d\n",
| MUSB_POWER_SOFTCONN
| MUSB_POWER_HSENAB
/* ENSUSPEND wedges tusb */
- // | MUSB_POWER_ENSUSPEND
+ /* | MUSB_POWER_ENSUSPEND */
);
musb->is_active = 0;
offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
- // assert(offset > 0)
+ /* assert(offset > 0) */
/* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
* be better than static MUSB_C_NUM_EPS and DYN_FIFO_SIZE...
ep_num = 1;
while (reg) {
if (reg & 1) {
- // musb_ep_select(musb->mregs, ep_num);
+ /* musb_ep_select(musb->mregs, ep_num); */
/* REVISIT just retval = ep->rx_irq(...) */
retval = IRQ_HANDLED;
if (devctl & MUSB_DEVCTL_HM) {
ep_num = 1;
while (reg) {
if (reg & 1) {
- // musb_ep_select(musb->mregs, ep_num);
+ /* musb_ep_select(musb->mregs, ep_num); */
/* REVISIT just retval |= ep->tx_irq(...) */
retval = IRQ_HANDLED;
if (devctl & MUSB_DEVCTL_HM) {
goto fail2;
}
musb->nIrq = nIrq;
-// FIXME this handles wakeup irqs wrong
+/* FIXME this handles wakeup irqs wrong */
if (enable_irq_wake(nIrq) == 0)
device_init_wakeup(dev, 1);
extern const char *otg_state_string(struct musb *);
-#endif // __MUSB_LINUX_DEBUG_H__
+#endif /* __MUSB_LINUX_DEBUG_H__ */
*/
struct dma_channel {
void *private_data;
- // FIXME not void* private_data, but a dma_controller *
+ /* FIXME not void* private_data, but a dma_controller * */
size_t max_len;
size_t actual_len;
enum dma_channel_status status;
MUSB_TXCSR_DMAMODE);
csr |= (MUSB_TXCSR_DMAENAB |
MUSB_TXCSR_MODE);
- // against programming guide
+ /* against programming guide */
}
else
csr |= (MUSB_TXCSR_AUTOSET
csr |= MUSB_RXCSR_DMAENAB;
#ifdef USE_MODE1
csr |= MUSB_RXCSR_AUTOCLEAR;
-// csr |= MUSB_RXCSR_DMAMODE;
+ /* csr |= MUSB_RXCSR_DMAMODE; */
/* this special sequence (enabling and then
* disabling MUSB_RXCSR_DMAMODE) is required
}
if (csr & MUSB_RXCSR_P_OVERRUN) {
- // csr |= MUSB_RXCSR_P_WZC_BITS;
+ /* csr |= MUSB_RXCSR_P_WZC_BITS; */
csr &= ~MUSB_RXCSR_P_OVERRUN;
musb_writew(epio, MUSB_RXCSR, csr);
{
DBG(2, "<= %s =>\n", __FUNCTION__);
- // FIXME iff driver's softconnect flag is set (as it is during probe,
- // though that can clear it), just musb_pullup().
+ /*
+ * FIXME iff driver's softconnect flag is set (as it is during probe,
+ * though that can clear it), just musb_pullup().
+ */
return -EINVAL;
}
.get_frame = musb_gadget_get_frame,
.wakeup = musb_gadget_wakeup,
.set_selfpowered = musb_gadget_set_self_powered,
- //.vbus_session = musb_gadget_vbus_session,
+ /* .vbus_session = musb_gadget_vbus_session, */
.vbus_draw = musb_gadget_vbus_draw,
.pullup = musb_gadget_pullup,
};
static void musb_gadget_release(struct device *dev)
{
- // kref_put(WHAT)
+ /* kref_put(WHAT) */
dev_dbg(dev, "%s\n", __FUNCTION__);
}
u8 fifo_count;
if (!request) {
- // WARN_ON(1);
+ /* WARN_ON(1); */
DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
return;
}
qh->frame = urb->start_frame;
/* enable SOF interrupt so we can count down */
DBG(1,"SOF for %d\n", epnum);
-#if 1 // ifndef CONFIG_ARCH_DAVINCI
+#if 1 /* ifndef CONFIG_ARCH_DAVINCI */
musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
#endif
}
int pipe = urb->pipe;
void *buffer = urb->transfer_buffer;
- // musb_ep_select(mbase, epnum);
+ /* musb_ep_select(mbase, epnum); */
rx_count = musb_readw(epio, MUSB_RXCOUNT);
DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
urb->transfer_buffer, qh->offset,
csr &= ~(MUSB_TXCSR_AUTOSET
| MUSB_TXCSR_DMAMODE);
csr |= (MUSB_TXCSR_DMAENAB);
- // against programming guide
+ /* against programming guide */
} else
csr |= (MUSB_TXCSR_AUTOSET
| MUSB_TXCSR_DMAENAB
musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
} else if (!(tx_csr & MUSB_TXCSR_DMAENAB)) {
- // WARN_ON(!buf);
+ /* WARN_ON(!buf); */
/* REVISIT: some docs say that when hw_ep->tx_double_buffered,
* (and presumably, fifo is not half-full) we should write TWO
status = -EPROTO;
ERR("Rx interrupt with no errors or packet!\n");
- // FIXME this is another "SHOULD NEVER HAPPEN"
+ /* FIXME this is another "SHOULD NEVER HAPPEN" */
-// SCRUB (RX)
+/* SCRUB (RX) */
/* do the proper sequence to abort the transfer */
musb_ep_select(mbase, epnum);
val &= ~MUSB_RXCSR_H_REQPKT;
.hub_control = musb_hub_control,
.bus_suspend = musb_bus_suspend,
.bus_resume = musb_bus_resume,
-// .start_port_reset = NULL,
-// .hub_irq_enable = NULL,
+ /* .start_port_reset = NULL, */
+ /* .hub_irq_enable = NULL, */
};
struct musb_hw_ep *hw_ep; /* current binding */
struct list_head ring; /* of musb_qh */
- //struct musb_qh *next; /* for periodic tree */
+ /* struct musb_qh *next; */ /* for periodic tree */
unsigned offset; /* in urb->transfer_buffer */
unsigned segsize; /* current xfer fragment */
reg = musb_readb(mbase, MUSB_DEVCTL);
reg |= MUSB_DEVCTL_HR;
musb_writeb(mbase, MUSB_DEVCTL, reg);
- //MUSB_HST_MODE( ((struct musb*)data) );
- //WARN("Host Mode\n");
+ /* MUSB_HST_MODE( ((struct musb*)data) ); */
+ /* WARN("Host Mode\n"); */
}
break;
}
/* generate the report for the end points */
- // REVISIT ... not unless something's connected!
+ /* REVISIT ... not unless something's connected! */
for (epnum = 0; count >= 0 && epnum < musb->nr_endpoints;
epnum++) {
code = dump_end_info(musb, epnum, buffer, count);
S_IFREG | S_IRUGO | S_IWUSR, NULL);
if (pde) {
pde->data = data;
- // pde->owner = THIS_MODULE;
+ /* pde->owner = THIS_MODULE; */
pde->read_proc = musb_proc_read;
pde->write_proc = musb_proc_write;
musb_writel(base, TUSB_PRCM_CONF, reg);
- // FIXME tusb6010_platform_retime(mode == 0);
+ /* FIXME tusb6010_platform_retime(mode == 0); */
}
/*
if ((is_otg_enabled(musb) && !musb->xceiv.default_a)
|| !is_host_enabled(musb)) {
#ifdef CONFIG_USB_MUSB_HDRC_HCD
- // ? musb_root_disconnect(musb);
+ /* ? musb_root_disconnect(musb); */
musb->port1_status &=
~(USB_PORT_STAT_CONNECTION
| USB_PORT_STAT_ENABLE
DBG(3, "wake %sactive %02x\n",
musb->is_active ? "" : "in", reg);
- // REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS
+ /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
}
if (int_src & TUSB_INT_SRC_USB_IP_CONN)
tusb_dma = container_of(c, struct tusb_omap_dma, controller);
- // DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch);
+ /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
return 0;
}
tusb_dma = container_of(c, struct tusb_omap_dma, controller);
- // DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch);
+ /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
return 0;
}