Different DPLL multiplier / divider pairs can result in frequencies
that are not exact matches of the values given by TI. When looking up
the table of known L4 / DSS1 values allow for a small difference.
Signed-off-by: Imre Deak <imre.deak@solidboot.com>
dss1_rate = clk_get_rate(rfbi.dss1_fck) / 1000000;
for (i = 0; i < ARRAY_SIZE(ftab); i++) {
- if (ftab[i].l4_clk == l4_rate &&
- ftab[i].dss1_clk == dss1_rate) {
+ /* Use a window instead of an exact match, to account
+ * for different DPLL multiplier / divider pairs.
+ */
+ if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
+ abs(ftab[i].dss1_clk - dss1_rate) < 3) {
min_l4_ticks = ftab[i].min_l4_ticks;
break;
}