omap2_clk_fixed_enable() was checking the wrong bit to determine if
the 54MHz APLL was ready, causing a "Clock apll54_ck didn't enable in
100000 tries" warning message on 2430SDP:
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
if (clk == &apll96_ck)
cval = OMAP24XX_ST_96M_APLL;
else if (clk == &apll54_ck)
- cval = OMAP24XX_ST_54M_CLK;
+ cval = OMAP24XX_ST_54M_APLL;
omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
clk->name);