]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
x86/PCI: irq and pci_ids patch for Intel Ibex Peak DeviceIDs
authorSeth Heasley <seth.heasley@intel.com>
Thu, 28 Aug 2008 22:40:59 +0000 (15:40 -0700)
committerJesse Barnes <jbarnes@virtuousgeek.org>
Mon, 20 Oct 2008 17:53:48 +0000 (10:53 -0700)
This patch updates the Intel Ibex Peak (PCH) LPC and SMBus Controller
DeviceIDs.

The LPC Controller ID is set by Firmware within the range of
0x3b00-3b1f.  This range is included in pci_ids.h using min and max
values, and irq.c now has code to handle the range (in lieu of 32
additions to a SWITCH statement).

The SMBus Controller ID is a fixed-value and will not change.

Signed-off-by: Seth Heasley <seth.heasley@intel.com>
Acked-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
arch/x86/pci/irq.c
include/linux/pci_ids.h

index 52a1de1128c1b4fff0dc80a04b82b8195f09f6fd..bf69dbe08bff66b19b8e9a7558d152fd4fce62f7 100644 (file)
@@ -590,13 +590,20 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route
        case PCI_DEVICE_ID_INTEL_ICH10_1:
        case PCI_DEVICE_ID_INTEL_ICH10_2:
        case PCI_DEVICE_ID_INTEL_ICH10_3:
-       case PCI_DEVICE_ID_INTEL_PCH_0:
-       case PCI_DEVICE_ID_INTEL_PCH_1:
                r->name = "PIIX/ICH";
                r->get = pirq_piix_get;
                r->set = pirq_piix_set;
                return 1;
        }
+
+       if ((device >= PCI_DEVICE_ID_INTEL_PCH_LPC_MIN) && 
+               (device <= PCI_DEVICE_ID_INTEL_PCH_LPC_MAX)) {
+               r->name = "PIIX/ICH";
+               r->get = pirq_piix_get;
+               r->set = pirq_piix_set;
+               return 1;
+       }
+
        return 0;
 }
 
index 8edddc240e4f61c133308d9af0af7da179b9c56b..e5d344bfcb7e584d91c6f8fc553900799ea9bbad 100644 (file)
 #define PCI_DEVICE_ID_INTEL_ICH10_3    0x3a1a
 #define PCI_DEVICE_ID_INTEL_ICH10_4    0x3a30
 #define PCI_DEVICE_ID_INTEL_ICH10_5    0x3a60
-#define PCI_DEVICE_ID_INTEL_PCH_0      0x3b10
-#define PCI_DEVICE_ID_INTEL_PCH_1      0x3b11
-#define PCI_DEVICE_ID_INTEL_PCH_2      0x3b30
+#define PCI_DEVICE_ID_INTEL_PCH_LPC_MIN        0x3b00
+#define PCI_DEVICE_ID_INTEL_PCH_LPC_MAX        0x3b1f
+#define PCI_DEVICE_ID_INTEL_PCH_SMBUS  0x3b30
 #define PCI_DEVICE_ID_INTEL_IOAT_SNB   0x402f
 #define PCI_DEVICE_ID_INTEL_5100_16    0x65f0
 #define PCI_DEVICE_ID_INTEL_5100_21    0x65f5