RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
.enable_bit = 0,
- .rate_offset= 8,
- .src_offset = 8,
+ .rate_offset = 8,
+ .src_offset = 8,
.recalc = &omap2_clksel_recalc,
};
RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
.enable_bit = 1,
- .src_offset = 13,
+ .src_offset = 13,
.recalc = &omap2_followparent_recalc,
};
CM_WKUP_SEL1,
.enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
.enable_bit = 0,
- .src_offset = 0,
+ .src_offset = 0,
.recalc = &omap2_followparent_recalc,
};
CM_CORE_SEL2,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
.enable_bit = 4,
- .src_offset = 2,
+ .src_offset = 2,
.recalc = &omap2_followparent_recalc,
};
CM_CORE_SEL2,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
.enable_bit = 5,
- .src_offset = 4,
+ .src_offset = 4,
.recalc = &omap2_followparent_recalc,
};
CM_CORE_SEL2,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
.enable_bit = 6,
- .src_offset = 6,
+ .src_offset = 6,
.recalc = &omap2_followparent_recalc,
};
CM_CORE_SEL2,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
.enable_bit = 7,
- .src_offset = 8,
+ .src_offset = 8,
.recalc = &omap2_followparent_recalc,
};
CM_CORE_SEL2,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
.enable_bit = 8,
- .src_offset = 10,
+ .src_offset = 10,
.recalc = &omap2_followparent_recalc,
};
CM_CORE_SEL2,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
.enable_bit = 9,
- .src_offset = 12,
+ .src_offset = 12,
.recalc = &omap2_followparent_recalc,
};
CM_CORE_SEL2,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
.enable_bit = 10,
- .src_offset = 14,
+ .src_offset = 14,
.recalc = &omap2_followparent_recalc,
};
CM_CORE_SEL2,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
.enable_bit = 11,
- .src_offset = 16,
+ .src_offset = 16,
.recalc = &omap2_followparent_recalc,
};
CM_CORE_SEL2,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
.enable_bit = 12,
- .src_offset = 18,
+ .src_offset = 18,
.recalc = &omap2_followparent_recalc,
};
CM_CORE_SEL2,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
.enable_bit = 13,
- .src_offset = 20,
+ .src_offset = 20,
.recalc = &omap2_followparent_recalc,
};
CM_CORE_SEL2,
.enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
.enable_bit = 14,
- .src_offset = 22,
+ .src_offset = 22,
.recalc = &omap2_followparent_recalc,
};