sdrc register defs

This patch adds some missing sdrc register definitions

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 5185a31122d567f322a9f61b2820dd238b580058..2c71461363424faabef6145e559ab9d711c88709 100644 (file)
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -165,9 +165,9 @@ omap3_cm_iclken1_core:
 omap3_sdrc_rfr_ctrl:
        .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 omap3_sdrc_actim_ctrla:
-       .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A)
+       .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
 omap3_sdrc_actim_ctrlb:
-       .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B)
+       .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
 omap3_sdrc_dlla_status:
        .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 omap3_sdrc_dlla_ctrl:

diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index 9cb1e2359e414837e04b772023895444d40783b9..b7db862806a806df3aa510e04cd643af758f7c41 100644 (file)
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -21,15 +21,24 @@
 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
 
 #define SDRC_SYSCONFIG         0x010
+#define SDRC_CS_CFG            0x040
+#define SDRC_SHARING           0x044
+#define SDRC_ERR_TYPE          0x04C
 #define SDRC_DLLA_CTRL         0x060
 #define SDRC_DLLA_STATUS       0x064
 #define SDRC_DLLB_CTRL         0x068
 #define SDRC_DLLB_STATUS       0x06C
 #define SDRC_POWER             0x070
+#define SDRC_MCFG_0            0x080
 #define SDRC_MR_0              0x084
-#define SDRC_ACTIM_CTRL_A      0x09c
-#define SDRC_ACTIM_CTRL_B      0x0a0
+#define SDRC_ACTIM_CTRL_A_0    0x09c
+#define SDRC_ACTIM_CTRL_B_0    0x0a0
 #define SDRC_RFR_CTRL_0                0x0a4
+#define SDRC_MCFG_1            0x0B0
+#define SDRC_MR_1              0x0B4
+#define SDRC_ACTIM_CTRL_A_1    0x0C4
+#define SDRC_ACTIM_CTRL_B_1    0x0C8
+#define SDRC_RFR_CTRL_1                0x0D4
 
 /*
  * These values represent the number of memory clock cycles between