#define MUSB_HSDMA_ADDRESS 0x8
#define MUSB_HSDMA_COUNT 0xc
-#define MGC_HSDMA_CHANNEL_OFFSET(_bChannel, _offset) \
+#define MUSB_HSDMA_CHANNEL_OFFSET(_bChannel, _offset) \
(MUSB_HSDMA_BASE + (_bChannel << 4) + _offset)
/* control register (16-bit): */
#define MUSB_HSDMA_BUSERROR_SHIFT 8
#define MUSB_HSDMA_BURSTMODE_SHIFT 9
#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
-#define MGC_HSDMA_BURSTMODE_UNSPEC 0
-#define MGC_HSDMA_BURSTMODE_INCR4 1
-#define MGC_HSDMA_BURSTMODE_INCR8 2
-#define MGC_HSDMA_BURSTMODE_INCR16 3
+#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
+#define MUSB_HSDMA_BURSTMODE_INCR4 1
+#define MUSB_HSDMA_BURSTMODE_INCR8 2
+#define MUSB_HSDMA_BURSTMODE_INCR16 3
-#define MGC_HSDMA_CHANNELS 8
+#define MUSB_HSDMA_CHANNELS 8
struct musb_dma_controller;
struct musb_dma_controller {
struct dma_controller Controller;
- struct musb_dma_channel aChannel[MGC_HSDMA_CHANNELS];
+ struct musb_dma_channel aChannel[MUSB_HSDMA_CHANNELS];
void *pDmaPrivate;
void __iomem *pCoreBase;
u8 bChannelCount;
dev_err(musb->controller,
"Stopping DMA controller while channel active\n");
- for (bBit = 0; bBit < MGC_HSDMA_CHANNELS; bBit++) {
+ for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) {
if (controller->bmUsedChannels & (1 << bBit)) {
pChannel = &(controller->aChannel[bBit].Channel);
dma_channel_release(pChannel);
struct musb_dma_controller *controller =
container_of(c, struct musb_dma_controller, Controller);
- for (bBit = 0; bBit < MGC_HSDMA_CHANNELS; bBit++) {
+ for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) {
if (!(controller->bmUsedChannels & (1 << bBit))) {
controller->bmUsedChannels |= (1 << bBit);
pImplChannel = &(controller->aChannel[bBit]);
}
if (packet_sz >= 64) {
csr |=
- MGC_HSDMA_BURSTMODE_INCR16 << MUSB_HSDMA_BURSTMODE_SHIFT;
+ MUSB_HSDMA_BURSTMODE_INCR16 << MUSB_HSDMA_BURSTMODE_SHIFT;
} else if (packet_sz >= 32) {
csr |=
- MGC_HSDMA_BURSTMODE_INCR8 << MUSB_HSDMA_BURSTMODE_SHIFT;
+ MUSB_HSDMA_BURSTMODE_INCR8 << MUSB_HSDMA_BURSTMODE_SHIFT;
} else if (packet_sz >= 16) {
csr |=
- MGC_HSDMA_BURSTMODE_INCR4 << MUSB_HSDMA_BURSTMODE_SHIFT;
+ MUSB_HSDMA_BURSTMODE_INCR4 << MUSB_HSDMA_BURSTMODE_SHIFT;
}
}
/* address/count */
musb_writel(mbase,
- MGC_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS),
+ MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS),
dma_addr);
musb_writel(mbase,
- MGC_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT),
+ MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT),
len);
/* control (this should start things) */
musb_writew(mbase,
- MGC_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL),
+ MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL),
csr);
}
}
musb_writew(mbase,
- MGC_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL), 0);
+ MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL), 0);
musb_writel(mbase,
- MGC_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS), 0);
+ MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS), 0);
musb_writel(mbase,
- MGC_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT), 0);
+ MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT), 0);
pChannel->status = MUSB_DMA_STATUS_FREE;
}
if (!int_hsdma)
goto done;
- for (bChannel = 0; bChannel < MGC_HSDMA_CHANNELS; bChannel++) {
+ for (bChannel = 0; bChannel < MUSB_HSDMA_CHANNELS; bChannel++) {
if (int_hsdma & (1 << bChannel)) {
pImplChannel = (struct musb_dma_channel *)
&(controller->aChannel[bChannel]);
pChannel = &pImplChannel->Channel;
csr = musb_readw(mbase,
- MGC_HSDMA_CHANNEL_OFFSET(bChannel,
+ MUSB_HSDMA_CHANNEL_OFFSET(bChannel,
MUSB_HSDMA_CONTROL));
if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
MUSB_DMA_STATUS_BUS_ABORT;
} else {
dwAddress = musb_readl(mbase,
- MGC_HSDMA_CHANNEL_OFFSET(
+ MUSB_HSDMA_CHANNEL_OFFSET(
bChannel,
MUSB_HSDMA_ADDRESS));
pChannel->actual_len =
GFP_KERNEL)))
return NULL;
- controller->bChannelCount = MGC_HSDMA_CHANNELS;
+ controller->bChannelCount = MUSB_HSDMA_CHANNELS;
controller->pDmaPrivate = musb;
controller->pCoreBase = pCoreBase;