]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
[POWERPC] 85xx: Convert dts to v1 syntax
authorKumar Gala <galak@kernel.crashing.org>
Thu, 17 Apr 2008 06:28:15 +0000 (01:28 -0500)
committerKumar Gala <galak@kernel.crashing.org>
Thu, 17 Apr 2008 06:28:15 +0000 (01:28 -0500)
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/boot/dts/mpc8540ads.dts
arch/powerpc/boot/dts/mpc8541cds.dts
arch/powerpc/boot/dts/mpc8544ds.dts
arch/powerpc/boot/dts/mpc8548cds.dts
arch/powerpc/boot/dts/mpc8555cds.dts
arch/powerpc/boot/dts/mpc8560ads.dts
arch/powerpc/boot/dts/mpc8568mds.dts
arch/powerpc/boot/dts/mpc8572ds.dts

index 975248491b7b9dcb258a5377781a07d0ae6ed12f..18033ed0b5356319332b71b035fbda62d87b25c5 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * MPC8540 ADS Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
        model = "MPC8540ADS";
 
                PowerPC,8540@0 {
                        device_type = "cpu";
-                       reg = <0>;
-                       d-cache-line-size = <20>;       // 32 bytes
-                       i-cache-line-size = <20>;       // 32 bytes
-                       d-cache-size = <8000>;          // L1, 32K
-                       i-cache-size = <8000>;          // L1, 32K
+                       reg = <0x0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
                        timebase-frequency = <0>;       //  33 MHz, from uboot
                        bus-frequency = <0>;    // 166 MHz
                        clock-frequency = <0>;  // 825 MHz, from uboot
 
        memory {
                device_type = "memory";
-               reg = <00000000 08000000>;      // 128M at 0x0
+               reg = <0x0 0x8000000>;  // 128M at 0x0
        };
 
        soc8540@e0000000 {
                #address-cells = <1>;
                #size-cells = <1>;
                device_type = "soc";
-               ranges = <0 e0000000 00100000>;
-               reg = <e0000000 00100000>;      // CCSRBAR 1M
+               ranges = <0x0 0xe0000000 0x100000>;
+               reg = <0xe0000000 0x100000>;    // CCSRBAR 1M
                bus-frequency = <0>;
 
                memory-controller@2000 {
                        compatible = "fsl,8540-memory-controller";
-                       reg = <2000 1000>;
+                       reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
-                       interrupts = <12 2>;
+                       interrupts = <18 2>;
                };
 
                l2-cache-controller@20000 {
                        compatible = "fsl,8540-l2-cache-controller";
-                       reg = <20000 1000>;
-                       cache-line-size = <20>; // 32 bytes
-                       cache-size = <40000>;   // L2, 256K
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x40000>; // L2, 256K
                        interrupt-parent = <&mpic>;
-                       interrupts = <10 2>;
+                       interrupts = <16 2>;
                };
 
                i2c@3000 {
@@ -76,8 +77,8 @@
                        #size-cells = <0>;
                        cell-index = <0>;
                        compatible = "fsl-i2c";
-                       reg = <3000 100>;
-                       interrupts = <2b 2>;
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
                        interrupt-parent = <&mpic>;
                        dfsrr;
                };
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "fsl,gianfar-mdio";
-                       reg = <24520 20>;
+                       reg = <0x24520 0x20>;
 
                        phy0: ethernet-phy@0 {
                                interrupt-parent = <&mpic>;
                                interrupts = <5 1>;
-                               reg = <0>;
+                               reg = <0x0>;
                                device_type = "ethernet-phy";
                        };
                        phy1: ethernet-phy@1 {
                                interrupt-parent = <&mpic>;
                                interrupts = <5 1>;
-                               reg = <1>;
+                               reg = <0x1>;
                                device_type = "ethernet-phy";
                        };
                        phy3: ethernet-phy@3 {
                                interrupt-parent = <&mpic>;
                                interrupts = <7 1>;
-                               reg = <3>;
+                               reg = <0x3>;
                                device_type = "ethernet-phy";
                        };
                };
                        device_type = "network";
                        model = "TSEC";
                        compatible = "gianfar";
-                       reg = <24000 1000>;
+                       reg = <0x24000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <1d 2 1e 2 22 2>;
+                       interrupts = <29 2 30 2 34 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy0>;
                };
                        device_type = "network";
                        model = "TSEC";
                        compatible = "gianfar";
-                       reg = <25000 1000>;
+                       reg = <0x25000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <23 2 24 2 28 2>;
+                       interrupts = <35 2 36 2 40 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy1>;
                };
                        device_type = "network";
                        model = "FEC";
                        compatible = "gianfar";
-                       reg = <26000 1000>;
+                       reg = <0x26000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <29 2>;
+                       interrupts = <41 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy3>;
                };
                        cell-index = <0>;
                        device_type = "serial";
                        compatible = "ns16550";
-                       reg = <4500 100>;       // reg base, size
+                       reg = <0x4500 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
-                       interrupts = <2a 2>;
+                       interrupts = <42 2>;
                        interrupt-parent = <&mpic>;
                };
 
                        cell-index = <1>;
                        device_type = "serial";
                        compatible = "ns16550";
-                       reg = <4600 100>;       // reg base, size
+                       reg = <0x4600 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
-                       interrupts = <2a 2>;
+                       interrupts = <42 2>;
                        interrupt-parent = <&mpic>;
                };
                mpic: pic@40000 {
                        interrupt-controller;
                        #address-cells = <0>;
                        #interrupt-cells = <2>;
-                       reg = <40000 40000>;
+                       reg = <0x40000 0x40000>;
                        compatible = "chrp,open-pic";
                        device_type = "open-pic";
                        big-endian;
 
        pci0: pci@e0008000 {
                cell-index = <0>;
-               interrupt-map-mask = <f800 0 0 7>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
                        /* IDSEL 0x02 */
-                       1000 0 0 1 &mpic 1 1
-                       1000 0 0 2 &mpic 2 1
-                       1000 0 0 3 &mpic 3 1
-                       1000 0 0 4 &mpic 4 1
+                       0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
+                       0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
+                       0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
+                       0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
 
                        /* IDSEL 0x03 */
-                       1800 0 0 1 &mpic 4 1
-                       1800 0 0 2 &mpic 1 1
-                       1800 0 0 3 &mpic 2 1
-                       1800 0 0 4 &mpic 3 1
+                       0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
+                       0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                        /* IDSEL 0x04 */
-                       2000 0 0 1 &mpic 3 1
-                       2000 0 0 2 &mpic 4 1
-                       2000 0 0 3 &mpic 1 1
-                       2000 0 0 4 &mpic 2 1
+                       0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
+                       0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
+                       0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
+                       0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
 
                        /* IDSEL 0x05 */
-                       2800 0 0 1 &mpic 2 1
-                       2800 0 0 2 &mpic 3 1
-                       2800 0 0 3 &mpic 4 1
-                       2800 0 0 4 &mpic 1 1
+                       0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
+                       0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
 
                        /* IDSEL 0x0c */
-                       6000 0 0 1 &mpic 1 1
-                       6000 0 0 2 &mpic 2 1
-                       6000 0 0 3 &mpic 3 1
-                       6000 0 0 4 &mpic 4 1
+                       0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
+                       0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
+                       0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
+                       0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
 
                        /* IDSEL 0x0d */
-                       6800 0 0 1 &mpic 4 1
-                       6800 0 0 2 &mpic 1 1
-                       6800 0 0 3 &mpic 2 1
-                       6800 0 0 4 &mpic 3 1
+                       0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
+                       0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                        /* IDSEL 0x0e */
-                       7000 0 0 1 &mpic 3 1
-                       7000 0 0 2 &mpic 4 1
-                       7000 0 0 3 &mpic 1 1
-                       7000 0 0 4 &mpic 2 1
+                       0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
+                       0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
+                       0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
+                       0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
 
                        /* IDSEL 0x0f */
-                       7800 0 0 1 &mpic 2 1
-                       7800 0 0 2 &mpic 3 1
-                       7800 0 0 3 &mpic 4 1
-                       7800 0 0 4 &mpic 1 1
+                       0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
+                       0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
 
                        /* IDSEL 0x12 */
-                       9000 0 0 1 &mpic 1 1
-                       9000 0 0 2 &mpic 2 1
-                       9000 0 0 3 &mpic 3 1
-                       9000 0 0 4 &mpic 4 1
+                       0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
+                       0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
+                       0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
+                       0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 
                        /* IDSEL 0x13 */
-                       9800 0 0 1 &mpic 4 1
-                       9800 0 0 2 &mpic 1 1
-                       9800 0 0 3 &mpic 2 1
-                       9800 0 0 4 &mpic 3 1
+                       0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
+                       0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                        /* IDSEL 0x14 */
-                       a000 0 0 1 &mpic 3 1
-                       a000 0 0 2 &mpic 4 1
-                       a000 0 0 3 &mpic 1 1
-                       a000 0 0 4 &mpic 2 1
+                       0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
+                       0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
+                       0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
+                       0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
 
                        /* IDSEL 0x15 */
-                       a800 0 0 1 &mpic 2 1
-                       a800 0 0 2 &mpic 3 1
-                       a800 0 0 3 &mpic 4 1
-                       a800 0 0 4 &mpic 1 1>;
+                       0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
+                       0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
                interrupt-parent = <&mpic>;
-               interrupts = <18 2>;
+               interrupts = <24 2>;
                bus-range = <0 0>;
-               ranges = <02000000 0 80000000 80000000 0 20000000
-                         01000000 0 00000000 e2000000 0 00100000>;
-               clock-frequency = <3f940aa>;
+               ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                         0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
+               clock-frequency = <66666666>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <e0008000 1000>;
+               reg = <0xe0008000 0x1000>;
                compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
                device_type = "pci";
        };
index fa8d9aaad157974645ac5988a9ce4d1fcc632217..663c7c50ca4552c90a9362e933305cd83e5ccda9 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * MPC8541 CDS Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
        model = "MPC8541CDS";
 
                PowerPC,8541@0 {
                        device_type = "cpu";
-                       reg = <0>;
-                       d-cache-line-size = <20>;       // 32 bytes
-                       i-cache-line-size = <20>;       // 32 bytes
-                       d-cache-size = <8000>;          // L1, 32K
-                       i-cache-size = <8000>;          // L1, 32K
+                       reg = <0x0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
                        timebase-frequency = <0>;       //  33 MHz, from uboot
                        bus-frequency = <0>;    // 166 MHz
                        clock-frequency = <0>;  // 825 MHz, from uboot
 
        memory {
                device_type = "memory";
-               reg = <00000000 08000000>;      // 128M at 0x0
+               reg = <0x0 0x8000000>;  // 128M at 0x0
        };
 
        soc8541@e0000000 {
                #address-cells = <1>;
                #size-cells = <1>;
                device_type = "soc";
-               ranges = <0 e0000000 00100000>;
-               reg = <e0000000 00001000>;      // CCSRBAR 1M
+               ranges = <0x0 0xe0000000 0x100000>;
+               reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
                bus-frequency = <0>;
 
                memory-controller@2000 {
                        compatible = "fsl,8541-memory-controller";
-                       reg = <2000 1000>;
+                       reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
-                       interrupts = <12 2>;
+                       interrupts = <18 2>;
                };
 
                l2-cache-controller@20000 {
                        compatible = "fsl,8541-l2-cache-controller";
-                       reg = <20000 1000>;
-                       cache-line-size = <20>; // 32 bytes
-                       cache-size = <40000>;   // L2, 256K
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x40000>; // L2, 256K
                        interrupt-parent = <&mpic>;
-                       interrupts = <10 2>;
+                       interrupts = <16 2>;
                };
 
                i2c@3000 {
@@ -76,8 +77,8 @@
                        #size-cells = <0>;
                        cell-index = <0>;
                        compatible = "fsl-i2c";
-                       reg = <3000 100>;
-                       interrupts = <2b 2>;
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
                        interrupt-parent = <&mpic>;
                        dfsrr;
                };
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "fsl,gianfar-mdio";
-                       reg = <24520 20>;
+                       reg = <0x24520 0x20>;
 
                        phy0: ethernet-phy@0 {
                                interrupt-parent = <&mpic>;
                                interrupts = <5 1>;
-                               reg = <0>;
+                               reg = <0x0>;
                                device_type = "ethernet-phy";
                        };
                        phy1: ethernet-phy@1 {
                                interrupt-parent = <&mpic>;
                                interrupts = <5 1>;
-                               reg = <1>;
+                               reg = <0x1>;
                                device_type = "ethernet-phy";
                        };
                };
                        device_type = "network";
                        model = "TSEC";
                        compatible = "gianfar";
-                       reg = <24000 1000>;
+                       reg = <0x24000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <1d 2 1e 2 22 2>;
+                       interrupts = <29 2 30 2 34 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy0>;
                };
                        device_type = "network";
                        model = "TSEC";
                        compatible = "gianfar";
-                       reg = <25000 1000>;
+                       reg = <0x25000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <23 2 24 2 28 2>;
+                       interrupts = <35 2 36 2 40 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy1>;
                };
                        cell-index = <0>;
                        device_type = "serial";
                        compatible = "ns16550";
-                       reg = <4500 100>;       // reg base, size
+                       reg = <0x4500 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
-                       interrupts = <2a 2>;
+                       interrupts = <42 2>;
                        interrupt-parent = <&mpic>;
                };
 
                        cell-index = <1>;
                        device_type = "serial";
                        compatible = "ns16550";
-                       reg = <4600 100>;       // reg base, size
+                       reg = <0x4600 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
-                       interrupts = <2a 2>;
+                       interrupts = <42 2>;
                        interrupt-parent = <&mpic>;
                };
 
                        interrupt-controller;
                        #address-cells = <0>;
                        #interrupt-cells = <2>;
-                       reg = <40000 40000>;
+                       reg = <0x40000 0x40000>;
                        compatible = "chrp,open-pic";
                        device_type = "open-pic";
                         big-endian;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
-                       reg = <919c0 30>;
+                       reg = <0x919c0 0x30>;
                        ranges;
 
                        muram@80000 {
                                #address-cells = <1>;
                                #size-cells = <1>;
-                               ranges = <0 80000 10000>;
+                               ranges = <0x0 0x80000 0x10000>;
 
                                data@0 {
                                        compatible = "fsl,cpm-muram-data";
-                                       reg = <0 2000 9000 1000>;
+                                       reg = <0x0 0x2000 0x9000 0x1000>;
                                };
                        };
 
                                compatible = "fsl,mpc8541-brg",
                                             "fsl,cpm2-brg",
                                             "fsl,cpm-brg";
-                               reg = <919f0 10 915f0 10>;
+                               reg = <0x919f0 0x10 0x915f0 0x10>;
                        };
 
                        cpmpic: pic@90c00 {
                                interrupt-controller;
                                #address-cells = <0>;
                                #interrupt-cells = <2>;
-                               interrupts = <2e 2>;
+                               interrupts = <46 2>;
                                interrupt-parent = <&mpic>;
-                               reg = <90c00 80>;
+                               reg = <0x90c00 0x80>;
                                compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
                        };
                };
 
        pci0: pci@e0008000 {
                cell-index = <0>;
-               interrupt-map-mask = <1f800 0 0 7>;
+               interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
                interrupt-map = <
 
                        /* IDSEL 0x10 */
-                       08000 0 0 1 &mpic 0 1
-                       08000 0 0 2 &mpic 1 1
-                       08000 0 0 3 &mpic 2 1
-                       08000 0 0 4 &mpic 3 1
+                       0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                        /* IDSEL 0x11 */
-                       08800 0 0 1 &mpic 0 1
-                       08800 0 0 2 &mpic 1 1
-                       08800 0 0 3 &mpic 2 1
-                       08800 0 0 4 &mpic 3 1
+                       0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                        /* IDSEL 0x12 (Slot 1) */
-                       09000 0 0 1 &mpic 0 1
-                       09000 0 0 2 &mpic 1 1
-                       09000 0 0 3 &mpic 2 1
-                       09000 0 0 4 &mpic 3 1
+                       0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                        /* IDSEL 0x13 (Slot 2) */
-                       09800 0 0 1 &mpic 1 1
-                       09800 0 0 2 &mpic 2 1
-                       09800 0 0 3 &mpic 3 1
-                       09800 0 0 4 &mpic 0 1
+                       0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
+                       0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
+                       0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
+                       0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
 
                        /* IDSEL 0x14 (Slot 3) */
-                       0a000 0 0 1 &mpic 2 1
-                       0a000 0 0 2 &mpic 3 1
-                       0a000 0 0 3 &mpic 0 1
-                       0a000 0 0 4 &mpic 1 1
+                       0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
+                       0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
 
                        /* IDSEL 0x15 (Slot 4) */
-                       0a800 0 0 1 &mpic 3 1
-                       0a800 0 0 2 &mpic 0 1
-                       0a800 0 0 3 &mpic 1 1
-                       0a800 0 0 4 &mpic 2 1
+                       0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
+                       0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
+                       0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
+                       0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
 
                        /* Bus 1 (Tundra Bridge) */
                        /* IDSEL 0x12 (ISA bridge) */
-                       19000 0 0 1 &mpic 0 1
-                       19000 0 0 2 &mpic 1 1
-                       19000 0 0 3 &mpic 2 1
-                       19000 0 0 4 &mpic 3 1>;
+                       0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
                interrupt-parent = <&mpic>;
-               interrupts = <18 2>;
+               interrupts = <24 2>;
                bus-range = <0 0>;
-               ranges = <02000000 0 80000000 80000000 0 20000000
-                         01000000 0 00000000 e2000000 0 00100000>;
-               clock-frequency = <3f940aa>;
+               ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                         0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
+               clock-frequency = <66666666>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <e0008000 1000>;
+               reg = <0xe0008000 0x1000>;
                compatible = "fsl,mpc8540-pci";
                device_type = "pci";
 
                i8259@19000 {
                        interrupt-controller;
                        device_type = "interrupt-controller";
-                       reg = <19000 0 0 0 1>;
+                       reg = <0x19000 0x0 0x0 0x0 0x1>;
                        #address-cells = <0>;
                        #interrupt-cells = <2>;
                        compatible = "chrp,iic";
 
        pci1: pci@e0009000 {
                cell-index = <1>;
-               interrupt-map-mask = <f800 0 0 7>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
                        /* IDSEL 0x15 */
-                       a800 0 0 1 &mpic b 1
-                       a800 0 0 2 &mpic b 1
-                       a800 0 0 3 &mpic b 1
-                       a800 0 0 4 &mpic b 1>;
+                       0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+                       0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
+                       0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
+                       0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
                interrupt-parent = <&mpic>;
-               interrupts = <19 2>;
+               interrupts = <25 2>;
                bus-range = <0 0>;
-               ranges = <02000000 0 a0000000 a0000000 0 20000000
-                         01000000 0 00000000 e3000000 0 00100000>;
-               clock-frequency = <3f940aa>;
+               ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+                         0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
+               clock-frequency = <66666666>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <e0009000 1000>;
+               reg = <0xe0009000 0x1000>;
                compatible = "fsl,mpc8540-pci";
                device_type = "pci";
        };
index 131ffaae2b5d7d42f850896f38b4cf32efd27d17..e238ebb4596eaf1da43732cb6bd6c15cd4462ad5 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * MPC8544 DS Device Tree Source
  *
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 / {
        model = "MPC8544DS";
        compatible = "MPC8544DS", "MPC85xxDS";
        };
 
        cpus {
-               #cpus = <1>;
+               #cpus = <0x1>;
                #address-cells = <1>;
                #size-cells = <0>;
 
                PowerPC,8544@0 {
                        device_type = "cpu";
-                       reg = <0>;
-                       d-cache-line-size = <20>;       // 32 bytes
-                       i-cache-line-size = <20>;       // 32 bytes
-                       d-cache-size = <8000>;          // L1, 32K
-                       i-cache-size = <8000>;          // L1, 32K
+                       reg = <0x0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
@@ -46,7 +47,7 @@
 
        memory {
                device_type = "memory";
-               reg = <00000000 00000000>;      // Filled by U-Boot
+               reg = <0x0 0x0>;        // Filled by U-Boot
        };
 
        soc8544@e0000000 {
                #size-cells = <1>;
                device_type = "soc";
 
-               ranges = <00000000 e0000000 00100000>;
-               reg = <e0000000 00001000>;      // CCSRBAR 1M
+               ranges = <0x0 0xe0000000 0x100000>;
+               reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
                bus-frequency = <0>;            // Filled out by uboot.
 
                memory-controller@2000 {
                        compatible = "fsl,8544-memory-controller";
-                       reg = <2000 1000>;
+                       reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
-                       interrupts = <12 2>;
+                       interrupts = <18 2>;
                };
 
                l2-cache-controller@20000 {
                        compatible = "fsl,8544-l2-cache-controller";
-                       reg = <20000 1000>;
-                       cache-line-size = <20>; // 32 bytes
-                       cache-size = <40000>;   // L2, 256K
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x40000>; // L2, 256K
                        interrupt-parent = <&mpic>;
-                       interrupts = <10 2>;
+                       interrupts = <16 2>;
                };
 
                i2c@3000 {
@@ -79,8 +80,8 @@
                        #size-cells = <0>;
                        cell-index = <0>;
                        compatible = "fsl-i2c";
-                       reg = <3000 100>;
-                       interrupts = <2b 2>;
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
                        interrupt-parent = <&mpic>;
                        dfsrr;
                };
@@ -90,8 +91,8 @@
                        #size-cells = <0>;
                        cell-index = <1>;
                        compatible = "fsl-i2c";
-                       reg = <3100 100>;
-                       interrupts = <2b 2>;
+                       reg = <0x3100 0x100>;
+                       interrupts = <43 2>;
                        interrupt-parent = <&mpic>;
                        dfsrr;
                };
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "fsl,gianfar-mdio";
-                       reg = <24520 20>;
+                       reg = <0x24520 0x20>;
 
                        phy0: ethernet-phy@0 {
                                interrupt-parent = <&mpic>;
-                               interrupts = <a 1>;
-                               reg = <0>;
+                               interrupts = <10 1>;
+                               reg = <0x0>;
                                device_type = "ethernet-phy";
                        };
                        phy1: ethernet-phy@1 {
                                interrupt-parent = <&mpic>;
-                               interrupts = <a 1>;
-                               reg = <1>;
+                               interrupts = <10 1>;
+                               reg = <0x1>;
                                device_type = "ethernet-phy";
                        };
                };
                        #address-cells = <1>;
                        #size-cells = <1>;
                        compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
-                       reg = <21300 4>;
-                       ranges = <0 21100 200>;
+                       reg = <0x21300 0x4>;
+                       ranges = <0x0 0x21100 0x200>;
                        cell-index = <0>;
                        dma-channel@0 {
                                compatible = "fsl,mpc8544-dma-channel",
                                                "fsl,eloplus-dma-channel";
-                               reg = <0 80>;
+                               reg = <0x0 0x80>;
                                cell-index = <0>;
                                interrupt-parent = <&mpic>;
-                               interrupts = <14 2>;
+                               interrupts = <20 2>;
                        };
                        dma-channel@80 {
                                compatible = "fsl,mpc8544-dma-channel",
                                                "fsl,eloplus-dma-channel";
-                               reg = <80 80>;
+                               reg = <0x80 0x80>;
                                cell-index = <1>;
                                interrupt-parent = <&mpic>;
-                               interrupts = <15 2>;
+                               interrupts = <21 2>;
                        };
                        dma-channel@100 {
                                compatible = "fsl,mpc8544-dma-channel",
                                                "fsl,eloplus-dma-channel";
-                               reg = <100 80>;
+                               reg = <0x100 0x80>;
                                cell-index = <2>;
                                interrupt-parent = <&mpic>;
-                               interrupts = <16 2>;
+                               interrupts = <22 2>;
                        };
                        dma-channel@180 {
                                compatible = "fsl,mpc8544-dma-channel",
                                                "fsl,eloplus-dma-channel";
-                               reg = <180 80>;
+                               reg = <0x180 0x80>;
                                cell-index = <3>;
                                interrupt-parent = <&mpic>;
-                               interrupts = <17 2>;
+                               interrupts = <23 2>;
                        };
                };
 
                        device_type = "network";
                        model = "TSEC";
                        compatible = "gianfar";
-                       reg = <24000 1000>;
+                       reg = <0x24000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <1d 2 1e 2 22 2>;
+                       interrupts = <29 2 30 2 34 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy0>;
                        phy-connection-type = "rgmii-id";
                        device_type = "network";
                        model = "TSEC";
                        compatible = "gianfar";
-                       reg = <26000 1000>;
+                       reg = <0x26000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <1f 2 20 2 21 2>;
+                       interrupts = <31 2 32 2 33 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy1>;
                        phy-connection-type = "rgmii-id";
                        cell-index = <0>;
                        device_type = "serial";
                        compatible = "ns16550";
-                       reg = <4500 100>;
+                       reg = <0x4500 0x100>;
                        clock-frequency = <0>;
-                       interrupts = <2a 2>;
+                       interrupts = <42 2>;
                        interrupt-parent = <&mpic>;
                };
 
                        cell-index = <1>;
                        device_type = "serial";
                        compatible = "ns16550";
-                       reg = <4600 100>;
+                       reg = <0x4600 0x100>;
                        clock-frequency = <0>;
-                       interrupts = <2a 2>;
+                       interrupts = <42 2>;
                        interrupt-parent = <&mpic>;
                };
 
                global-utilities@e0000 {        //global utilities block
                        compatible = "fsl,mpc8548-guts";
-                       reg = <e0000 1000>;
+                       reg = <0xe0000 0x1000>;
                        fsl,has-rstcr;
                };
 
                        interrupt-controller;
                        #address-cells = <0>;
                        #interrupt-cells = <2>;
-                       reg = <40000 40000>;
+                       reg = <0x40000 0x40000>;
                        compatible = "chrp,open-pic";
                        device_type = "open-pic";
                        big-endian;
                cell-index = <0>;
                compatible = "fsl,mpc8540-pci";
                device_type = "pci";
-               interrupt-map-mask = <f800 0 0 7>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
                        /* IDSEL 0x11 J17 Slot 1 */
-                       8800 0 0 1 &mpic 2 1
-                       8800 0 0 2 &mpic 3 1
-                       8800 0 0 3 &mpic 4 1
-                       8800 0 0 4 &mpic 1 1
+                       0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
+                       0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
 
                        /* IDSEL 0x12 J16 Slot 2 */
 
-                       9000 0 0 1 &mpic 3 1
-                       9000 0 0 2 &mpic 4 1
-                       9000 0 0 3 &mpic 2 1
-                       9000 0 0 4 &mpic 1 1>;
+                       0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
+                       0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
+                       0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
 
                interrupt-parent = <&mpic>;
-               interrupts = <18 2>;
-               bus-range = <0 ff>;
-               ranges = <02000000 0 c0000000 c0000000 0 20000000
-                         01000000 0 00000000 e1000000 0 00010000>;
-               clock-frequency = <3f940aa>;
+               interrupts = <24 2>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
+                         0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
+               clock-frequency = <66666666>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <e0008000 1000>;
+               reg = <0xe0008000 0x1000>;
        };
 
        pci1: pcie@e0009000 {
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <e0009000 1000>;
-               bus-range = <0 ff>;
-               ranges = <02000000 0 80000000 80000000 0 20000000
-                         01000000 0 00000000 e1010000 0 00010000>;
-               clock-frequency = <1fca055>;
+               reg = <0xe0009000 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                         0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
+               clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
-               interrupts = <1a 2>;
-               interrupt-map-mask = <f800 0 0 7>;
+               interrupts = <26 2>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x0 */
-                       0000 0 0 1 &mpic 4 1
-                       0000 0 0 2 &mpic 5 1
-                       0000 0 0 3 &mpic 6 1
-                       0000 0 0 4 &mpic 7 1
+                       0000 0x0 0x0 0x1 &mpic 0x4 0x1
+                       0000 0x0 0x0 0x2 &mpic 0x5 0x1
+                       0000 0x0 0x0 0x3 &mpic 0x6 0x1
+                       0000 0x0 0x0 0x4 &mpic 0x7 0x1
                        >;
                pcie@0 {
-                       reg = <0 0 0 0 0>;
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                       ranges = <02000000 0 80000000
-                                 02000000 0 80000000
-                                 0 20000000
+                       ranges = <0x2000000 0x0 0x80000000
+                                 0x2000000 0x0 0x80000000
+                                 0x0 0x20000000
 
-                                 01000000 0 00000000
-                                 01000000 0 00000000
-                                 0 00010000>;
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x10000>;
                };
        };
 
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <e000a000 1000>;
-               bus-range = <0 ff>;
-               ranges = <02000000 0 a0000000 a0000000 0 10000000
-                         01000000 0 00000000 e1020000 0 00010000>;
-               clock-frequency = <1fca055>;
+               reg = <0xe000a000 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
+                         0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
+               clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
-               interrupts = <19 2>;
-               interrupt-map-mask = <f800 0 0 7>;
+               interrupts = <25 2>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x0 */
-                       0000 0 0 1 &mpic 0 1
-                       0000 0 0 2 &mpic 1 1
-                       0000 0 0 3 &mpic 2 1
-                       0000 0 0 4 &mpic 3 1
+                       0000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0000 0x0 0x0 0x4 &mpic 0x3 0x1
                        >;
                pcie@0 {
-                       reg = <0 0 0 0 0>;
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                       ranges = <02000000 0 a0000000
-                                 02000000 0 a0000000
-                                 0 10000000
+                       ranges = <0x2000000 0x0 0xa0000000
+                                 0x2000000 0x0 0xa0000000
+                                 0x0 0x10000000
 
-                                 01000000 0 00000000
-                                 01000000 0 00000000
-                                 0 00010000>;
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x10000>;
                };
        };
 
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <e000b000 1000>;
-               bus-range = <0 ff>;
-               ranges = <02000000 0 b0000000 b0000000 0 00100000
-                         01000000 0 00000000 b0100000 0 00100000>;
-               clock-frequency = <1fca055>;
+               reg = <0xe000b000 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
+                         0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
+               clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
-               interrupts = <1b 2>;
-               interrupt-map-mask = <ff00 0 0 1>;
+               interrupts = <27 2>;
+               interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
                interrupt-map = <
                        // IDSEL 0x1c  USB
-                       e000 0 0 1 &i8259 c 2
-                       e100 0 0 2 &i8259 9 2
-                       e200 0 0 3 &i8259 a 2
-                       e300 0 0 4 &i8259 b 2
+                       0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
+                       0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
+                       0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
+                       0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 
                        // IDSEL 0x1d  Audio
-                       e800 0 0 1 &i8259 6 2
+                       0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 
                        // IDSEL 0x1e Legacy
-                       f000 0 0 1 &i8259 7 2
-                       f100 0 0 1 &i8259 7 2
+                       0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+                       0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 
                        // IDSEL 0x1f IDE/SATA
-                       f800 0 0 1 &i8259 e 2
-                       f900 0 0 1 &i8259 5 2
+                       0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+                       0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
                >;
 
                pcie@0 {
-                       reg = <0 0 0 0 0>;
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                       ranges = <02000000 0 b0000000
-                                 02000000 0 b0000000
-                                 0 00100000
+                       ranges = <0x2000000 0x0 0xb0000000
+                                 0x2000000 0x0 0xb0000000
+                                 0x0 0x100000
 
-                                 01000000 0 00000000
-                                 01000000 0 00000000
-                                 0 00100000>;
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x100000>;
 
                        uli1575@0 {
-                               reg = <0 0 0 0 0>;
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
                                #size-cells = <2>;
                                #address-cells = <3>;
-                               ranges = <02000000 0 b0000000
-                                         02000000 0 b0000000
-                                         0 00100000
+                               ranges = <0x2000000 0x0 0xb0000000
+                                         0x2000000 0x0 0xb0000000
+                                         0x0 0x100000
 
-                                         01000000 0 00000000
-                                         01000000 0 00000000
-                                         0 00100000>;
+                                         0x1000000 0x0 0x0
+                                         0x1000000 0x0 0x0
+                                         0x0 0x100000>;
                                isa@1e {
                                        device_type = "isa";
                                        #interrupt-cells = <2>;
                                        #size-cells = <1>;
                                        #address-cells = <2>;
-                                       reg = <f000 0 0 0 0>;
-                                       ranges = <0
-                                                 01000000 0 0
-                                                 00001000>;
+                                       reg = <0xf000 0x0 0x0 0x0 0x0>;
+                                       ranges = <0x1 0x0
+                                                 0x1000000 0x0 0x0
+                                                 0x1000>;
                                        interrupt-parent = <&i8259>;
 
                                        i8259: interrupt-controller@20 {
-                                               reg = <1 20 2
-                                                      1 a0 2
-                                                      1 4d0 2>;
+                                               reg = <0x1 0x20 0x2
+                                                      0x1 0xa0 0x2
+                                                      0x1 0x4d0 0x2>;
                                                interrupt-controller;
                                                device_type = "interrupt-controller";
                                                #address-cells = <0>;
                                        i8042@60 {
                                                #size-cells = <0>;
                                                #address-cells = <1>;
-                                               reg = <1 60 1 1 64 1>;
-                                               interrupts = <1 3 c 3>;
+                                               reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+                                               interrupts = <1 3 12 3>;
                                                interrupt-parent = <&i8259>;
 
                                                keyboard@0 {
-                                                       reg = <0>;
+                                                       reg = <0x0>;
                                                        compatible = "pnpPNP,303";
                                                };
 
                                                mouse@1 {
-                                                       reg = <1>;
+                                                       reg = <0x1>;
                                                        compatible = "pnpPNP,f03";
                                                };
                                        };
 
                                        rtc@70 {
                                                compatible = "pnpPNP,b00";
-                                               reg = <1 70 2>;
+                                               reg = <0x1 0x70 0x2>;
                                        };
 
                                        gpio@400 {
-                                               reg = <1 400 80>;
+                                               reg = <0x1 0x400 0x80>;
                                        };
                                };
                        };
index 1f470c6a1c63cf89a08452196862e5d5e149d0ea..fa298a8c81cc11c12d753375d467276f554a5754 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * MPC8548 CDS Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
        model = "MPC8548CDS";
 
                PowerPC,8548@0 {
                        device_type = "cpu";
-                       reg = <0>;
-                       d-cache-line-size = <20>;       // 32 bytes
-                       i-cache-line-size = <20>;       // 32 bytes
-                       d-cache-size = <8000>;          // L1, 32K
-                       i-cache-size = <8000>;          // L1, 32K
+                       reg = <0x0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
                        timebase-frequency = <0>;       //  33 MHz, from uboot
                        bus-frequency = <0>;    // 166 MHz
                        clock-frequency = <0>;  // 825 MHz, from uboot
 
        memory {
                device_type = "memory";
-               reg = <00000000 08000000>;      // 128M at 0x0
+               reg = <0x0 0x8000000>;  // 128M at 0x0
        };
 
        soc8548@e0000000 {
                #address-cells = <1>;
                #size-cells = <1>;
                device_type = "soc";
-               ranges = <00000000 e0000000 00100000>;
-               reg = <e0000000 00001000>;      // CCSRBAR
+               ranges = <0x0 0xe0000000 0x100000>;
+               reg = <0xe0000000 0x1000>;      // CCSRBAR
                bus-frequency = <0>;
 
                memory-controller@2000 {
                        compatible = "fsl,8548-memory-controller";
-                       reg = <2000 1000>;
+                       reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
-                       interrupts = <12 2>;
+                       interrupts = <18 2>;
                };
 
                l2-cache-controller@20000 {
                        compatible = "fsl,8548-l2-cache-controller";
-                       reg = <20000 1000>;
-                       cache-line-size = <20>; // 32 bytes
-                       cache-size = <80000>;   // L2, 512K
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x80000>; // L2, 512K
                        interrupt-parent = <&mpic>;
-                       interrupts = <10 2>;
+                       interrupts = <16 2>;
                };
 
                i2c@3000 {
@@ -81,8 +82,8 @@
                        #size-cells = <0>;
                        cell-index = <0>;
                        compatible = "fsl-i2c";
-                       reg = <3000 100>;
-                       interrupts = <2b 2>;
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
                        interrupt-parent = <&mpic>;
                        dfsrr;
                };
@@ -92,8 +93,8 @@
                        #size-cells = <0>;
                        cell-index = <1>;
                        compatible = "fsl-i2c";
-                       reg = <3100 100>;
-                       interrupts = <2b 2>;
+                       reg = <0x3100 0x100>;
+                       interrupts = <43 2>;
                        interrupt-parent = <&mpic>;
                        dfsrr;
                };
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "fsl,gianfar-mdio";
-                       reg = <24520 20>;
+                       reg = <0x24520 0x20>;
 
                        phy0: ethernet-phy@0 {
                                interrupt-parent = <&mpic>;
                                interrupts = <5 1>;
-                               reg = <0>;
+                               reg = <0x0>;
                                device_type = "ethernet-phy";
                        };
                        phy1: ethernet-phy@1 {
                                interrupt-parent = <&mpic>;
                                interrupts = <5 1>;
-                               reg = <1>;
+                               reg = <0x1>;
                                device_type = "ethernet-phy";
                        };
                        phy2: ethernet-phy@2 {
                                interrupt-parent = <&mpic>;
                                interrupts = <5 1>;
-                               reg = <2>;
+                               reg = <0x2>;
                                device_type = "ethernet-phy";
                        };
                        phy3: ethernet-phy@3 {
                                interrupt-parent = <&mpic>;
                                interrupts = <5 1>;
-                               reg = <3>;
+                               reg = <0x3>;
                                device_type = "ethernet-phy";
                        };
                };
                        device_type = "network";
                        model = "eTSEC";
                        compatible = "gianfar";
-                       reg = <24000 1000>;
+                       reg = <0x24000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <1d 2 1e 2 22 2>;
+                       interrupts = <29 2 30 2 34 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy0>;
                };
                        device_type = "network";
                        model = "eTSEC";
                        compatible = "gianfar";
-                       reg = <25000 1000>;
+                       reg = <0x25000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <23 2 24 2 28 2>;
+                       interrupts = <35 2 36 2 40 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy1>;
                };
                        device_type = "network";
                        model = "eTSEC";
                        compatible = "gianfar";
-                       reg = <26000 1000>;
+                       reg = <0x26000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <1f 2 20 2 21 2>;
+                       interrupts = <31 2 32 2 33 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy2>;
                };
                        device_type = "network";
                        model = "eTSEC";
                        compatible = "gianfar";
-                       reg = <27000 1000>;
+                       reg = <0x27000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <25 2 26 2 27 2>;
+                       interrupts = <37 2 38 2 39 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy3>;
                };
                        cell-index = <0>;
                        device_type = "serial";
                        compatible = "ns16550";
-                       reg = <4500 100>;       // reg base, size
+                       reg = <0x4500 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
-                       interrupts = <2a 2>;
+                       interrupts = <42 2>;
                        interrupt-parent = <&mpic>;
                };
 
                        cell-index = <1>;
                        device_type = "serial";
                        compatible = "ns16550";
-                       reg = <4600 100>;       // reg base, size
+                       reg = <0x4600 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
-                       interrupts = <2a 2>;
+                       interrupts = <42 2>;
                        interrupt-parent = <&mpic>;
                };
 
                global-utilities@e0000 {        //global utilities reg
                        compatible = "fsl,mpc8548-guts";
-                       reg = <e0000 1000>;
+                       reg = <0xe0000 0x1000>;
                        fsl,has-rstcr;
                };
 
                        interrupt-controller;
                        #address-cells = <0>;
                        #interrupt-cells = <2>;
-                       reg = <40000 40000>;
+                       reg = <0x40000 0x40000>;
                        compatible = "chrp,open-pic";
                        device_type = "open-pic";
                         big-endian;
 
        pci0: pci@e0008000 {
                cell-index = <0>;
-               interrupt-map-mask = <f800 0 0 7>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x4 (PCIX Slot 2) */
-                       02000 0 0 1 &mpic 0 1
-                       02000 0 0 2 &mpic 1 1
-                       02000 0 0 3 &mpic 2 1
-                       02000 0 0 4 &mpic 3 1
+                       0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                        /* IDSEL 0x5 (PCIX Slot 3) */
-                       02800 0 0 1 &mpic 1 1
-                       02800 0 0 2 &mpic 2 1
-                       02800 0 0 3 &mpic 3 1
-                       02800 0 0 4 &mpic 0 1
+                       0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
+                       0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
+                       0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
+                       0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
 
                        /* IDSEL 0x6 (PCIX Slot 4) */
-                       03000 0 0 1 &mpic 2 1
-                       03000 0 0 2 &mpic 3 1
-                       03000 0 0 3 &mpic 0 1
-                       03000 0 0 4 &mpic 1 1
+                       0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
+                       0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 
                        /* IDSEL 0x8 (PCIX Slot 5) */
-                       04000 0 0 1 &mpic 0 1
-                       04000 0 0 2 &mpic 1 1
-                       04000 0 0 3 &mpic 2 1
-                       04000 0 0 4 &mpic 3 1
+                       0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                        /* IDSEL 0xC (Tsi310 bridge) */
-                       06000 0 0 1 &mpic 0 1
-                       06000 0 0 2 &mpic 1 1
-                       06000 0 0 3 &mpic 2 1
-                       06000 0 0 4 &mpic 3 1
+                       0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                        /* IDSEL 0x14 (Slot 2) */
-                       0a000 0 0 1 &mpic 0 1
-                       0a000 0 0 2 &mpic 1 1
-                       0a000 0 0 3 &mpic 2 1
-                       0a000 0 0 4 &mpic 3 1
+                       0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                        /* IDSEL 0x15 (Slot 3) */
-                       0a800 0 0 1 &mpic 1 1
-                       0a800 0 0 2 &mpic 2 1
-                       0a800 0 0 3 &mpic 3 1
-                       0a800 0 0 4 &mpic 0 1
+                       0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
+                       0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
+                       0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
+                       0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
 
                        /* IDSEL 0x16 (Slot 4) */
-                       0b000 0 0 1 &mpic 2 1
-                       0b000 0 0 2 &mpic 3 1
-                       0b000 0 0 3 &mpic 0 1
-                       0b000 0 0 4 &mpic 1 1
+                       0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
+                       0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
 
                        /* IDSEL 0x18 (Slot 5) */
-                       0c000 0 0 1 &mpic 0 1
-                       0c000 0 0 2 &mpic 1 1
-                       0c000 0 0 3 &mpic 2 1
-                       0c000 0 0 4 &mpic 3 1
+                       0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                        /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
-                       0E000 0 0 1 &mpic 0 1
-                       0E000 0 0 2 &mpic 1 1
-                       0E000 0 0 3 &mpic 2 1
-                       0E000 0 0 4 &mpic 3 1>;
+                       0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 
                interrupt-parent = <&mpic>;
-               interrupts = <18 2>;
+               interrupts = <24 2>;
                bus-range = <0 0>;
-               ranges = <02000000 0 80000000 80000000 0 10000000
-                         01000000 0 00000000 e2000000 0 00800000>;
-               clock-frequency = <3f940aa>;
+               ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
+                         0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
+               clock-frequency = <66666666>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <e0008000 1000>;
+               reg = <0xe0008000 0x1000>;
                compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
                device_type = "pci";
 
                pci_bridge@1c {
-                       interrupt-map-mask = <f800 0 0 7>;
+                       interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                        interrupt-map = <
 
                                /* IDSEL 0x00 (PrPMC Site) */
-                               0000 0 0 1 &mpic 0 1
-                               0000 0 0 2 &mpic 1 1
-                               0000 0 0 3 &mpic 2 1
-                               0000 0 0 4 &mpic 3 1
+                               0000 0x0 0x0 0x1 &mpic 0x0 0x1
+                               0000 0x0 0x0 0x2 &mpic 0x1 0x1
+                               0000 0x0 0x0 0x3 &mpic 0x2 0x1
+                               0000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                                /* IDSEL 0x04 (VIA chip) */
-                               2000 0 0 1 &mpic 0 1
-                               2000 0 0 2 &mpic 1 1
-                               2000 0 0 3 &mpic 2 1
-                               2000 0 0 4 &mpic 3 1
+                               0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
+                               0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
+                               0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
+                               0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                                /* IDSEL 0x05 (8139) */
-                               2800 0 0 1 &mpic 1 1
+                               0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
 
                                /* IDSEL 0x06 (Slot 6) */
-                               3000 0 0 1 &mpic 2 1
-                               3000 0 0 2 &mpic 3 1
-                               3000 0 0 3 &mpic 0 1
-                               3000 0 0 4 &mpic 1 1
+                               0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
+                               0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
+                               0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
+                               0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 
                                /* IDESL 0x07 (Slot 7) */
-                               3800 0 0 1 &mpic 3 1
-                               3800 0 0 2 &mpic 0 1
-                               3800 0 0 3 &mpic 1 1
-                               3800 0 0 4 &mpic 2 1>;
+                               0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
+                               0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
+                               0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
+                               0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
 
-                       reg = <e000 0 0 0 0>;
+                       reg = <0xe000 0x0 0x0 0x0 0x0>;
                        #interrupt-cells = <1>;
                        #size-cells = <2>;
                        #address-cells = <3>;
-                       ranges = <02000000 0 80000000
-                                 02000000 0 80000000
-                                 0 20000000
-                                 01000000 0 00000000
-                                 01000000 0 00000000
-                                 0 00080000>;
-                       clock-frequency = <1fca055>;
+                       ranges = <0x2000000 0x0 0x80000000
+                                 0x2000000 0x0 0x80000000
+                                 0x0 0x20000000
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x80000>;
+                       clock-frequency = <33333333>;
 
                        isa@4 {
                                device_type = "isa";
                                #interrupt-cells = <2>;
                                #size-cells = <1>;
                                #address-cells = <2>;
-                               reg = <2000 0 0 0 0>;
-                               ranges = <1 0 01000000 0 0 00001000>;
+                               reg = <0x2000 0x0 0x0 0x0 0x0>;
+                               ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
                                interrupt-parent = <&i8259>;
 
                                i8259: interrupt-controller@20 {
                                        interrupt-controller;
                                        device_type = "interrupt-controller";
-                                       reg = <1 20 2
-                                              1 a0 2
-                                              1 4d0 2>;
+                                       reg = <0x1 0x20 0x2
+                                              0x1 0xa0 0x2
+                                              0x1 0x4d0 0x2>;
                                        #address-cells = <0>;
                                        #interrupt-cells = <2>;
                                        compatible = "chrp,iic";
 
                                rtc@70 {
                                        compatible = "pnpPNP,b00";
-                                       reg = <1 70 2>;
+                                       reg = <0x1 0x70 0x2>;
                                };
                        };
                };
 
        pci1: pci@e0009000 {
                cell-index = <1>;
-               interrupt-map-mask = <f800 0 0 7>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
                        /* IDSEL 0x15 */
-                       a800 0 0 1 &mpic b 1
-                       a800 0 0 2 &mpic 1 1
-                       a800 0 0 3 &mpic 2 1
-                       a800 0 0 4 &mpic 3 1>;
+                       0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+                       0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
 
                interrupt-parent = <&mpic>;
-               interrupts = <19 2>;
+               interrupts = <25 2>;
                bus-range = <0 0>;
-               ranges = <02000000 0 90000000 90000000 0 10000000
-                         01000000 0 00000000 e2800000 0 00800000>;
-               clock-frequency = <3f940aa>;
+               ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
+                         0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
+               clock-frequency = <66666666>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <e0009000 1000>;
+               reg = <0xe0009000 0x1000>;
                compatible = "fsl,mpc8540-pci";
                device_type = "pci";
        };
 
        pci2: pcie@e000a000 {
                cell-index = <2>;
-               interrupt-map-mask = <f800 0 0 7>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
                        /* IDSEL 0x0 (PEX) */
-                       00000 0 0 1 &mpic 0 1
-                       00000 0 0 2 &mpic 1 1
-                       00000 0 0 3 &mpic 2 1
-                       00000 0 0 4 &mpic 3 1>;
+                       00000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       00000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       00000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 
                interrupt-parent = <&mpic>;
-               interrupts = <1a 2>;
-               bus-range = <0 ff>;
-               ranges = <02000000 0 a0000000 a0000000 0 20000000
-                         01000000 0 00000000 e3000000 0 08000000>;
-               clock-frequency = <1fca055>;
+               interrupts = <26 2>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+                         0x1000000 0x0 0x0 0xe3000000 0x0 0x8000000>;
+               clock-frequency = <33333333>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <e000a000 1000>;
+               reg = <0xe000a000 0x1000>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                pcie@0 {
-                       reg = <0 0 0 0 0>;
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                       ranges = <02000000 0 a0000000
-                                 02000000 0 a0000000
-                                 0 20000000
+                       ranges = <0x2000000 0x0 0xa0000000
+                                 0x2000000 0x0 0xa0000000
+                                 0x0 0x20000000
 
-                                 01000000 0 00000000
-                                 01000000 0 00000000
-                                 0 08000000>;
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x8000000>;
                };
        };
 };
index 4538f3c388629cd68da8ed93914e8ee2f82e4d9f..b025c566c10d1cf725a3675d113f0efb6c73c940 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * MPC8555 CDS Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
        model = "MPC8555CDS";
 
                PowerPC,8555@0 {
                        device_type = "cpu";
-                       reg = <0>;
-                       d-cache-line-size = <20>;       // 32 bytes
-                       i-cache-line-size = <20>;       // 32 bytes
-                       d-cache-size = <8000>;          // L1, 32K
-                       i-cache-size = <8000>;          // L1, 32K
+                       reg = <0x0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
                        timebase-frequency = <0>;       //  33 MHz, from uboot
                        bus-frequency = <0>;    // 166 MHz
                        clock-frequency = <0>;  // 825 MHz, from uboot
 
        memory {
                device_type = "memory";
-               reg = <00000000 08000000>;      // 128M at 0x0
+               reg = <0x0 0x8000000>;  // 128M at 0x0
        };
 
        soc8555@e0000000 {
                #address-cells = <1>;
                #size-cells = <1>;
                device_type = "soc";
-               ranges = <0 e0000000 00100000>;
-               reg = <e0000000 00001000>;      // CCSRBAR 1M
+               ranges = <0x0 0xe0000000 0x100000>;
+               reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
                bus-frequency = <0>;
 
                memory-controller@2000 {
                        compatible = "fsl,8555-memory-controller";
-                       reg = <2000 1000>;
+                       reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
-                       interrupts = <12 2>;
+                       interrupts = <18 2>;
                };
 
                l2-cache-controller@20000 {
                        compatible = "fsl,8555-l2-cache-controller";
-                       reg = <20000 1000>;
-                       cache-line-size = <20>; // 32 bytes
-                       cache-size = <40000>;   // L2, 256K
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x40000>; // L2, 256K
                        interrupt-parent = <&mpic>;
-                       interrupts = <10 2>;
+                       interrupts = <16 2>;
                };
 
                i2c@3000 {
@@ -76,8 +77,8 @@
                        #size-cells = <0>;
                        cell-index = <0>;
                        compatible = "fsl-i2c";
-                       reg = <3000 100>;
-                       interrupts = <2b 2>;
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
                        interrupt-parent = <&mpic>;
                        dfsrr;
                };
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "fsl,gianfar-mdio";
-                       reg = <24520 20>;
+                       reg = <0x24520 0x20>;
 
                        phy0: ethernet-phy@0 {
                                interrupt-parent = <&mpic>;
                                interrupts = <5 1>;
-                               reg = <0>;
+                               reg = <0x0>;
                                device_type = "ethernet-phy";
                        };
                        phy1: ethernet-phy@1 {
                                interrupt-parent = <&mpic>;
                                interrupts = <5 1>;
-                               reg = <1>;
+                               reg = <0x1>;
                                device_type = "ethernet-phy";
                        };
                };
                        device_type = "network";
                        model = "TSEC";
                        compatible = "gianfar";
-                       reg = <24000 1000>;
+                       reg = <0x24000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <1d 2 1e 2 22 2>;
+                       interrupts = <29 2 30 2 34 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy0>;
                };
                        device_type = "network";
                        model = "TSEC";
                        compatible = "gianfar";
-                       reg = <25000 1000>;
+                       reg = <0x25000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <23 2 24 2 28 2>;
+                       interrupts = <35 2 36 2 40 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy1>;
                };
                        cell-index = <0>;
                        device_type = "serial";
                        compatible = "ns16550";
-                       reg = <4500 100>;       // reg base, size
+                       reg = <0x4500 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
-                       interrupts = <2a 2>;
+                       interrupts = <42 2>;
                        interrupt-parent = <&mpic>;
                };
 
                        cell-index = <1>;
                        device_type = "serial";
                        compatible = "ns16550";
-                       reg = <4600 100>;       // reg base, size
+                       reg = <0x4600 0x100>;   // reg base, size
                        clock-frequency = <0>;  // should we fill in in uboot?
-                       interrupts = <2a 2>;
+                       interrupts = <42 2>;
                        interrupt-parent = <&mpic>;
                };
 
                        interrupt-controller;
                        #address-cells = <0>;
                        #interrupt-cells = <2>;
-                       reg = <40000 40000>;
+                       reg = <0x40000 0x40000>;
                        compatible = "chrp,open-pic";
                        device_type = "open-pic";
                         big-endian;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
-                       reg = <919c0 30>;
+                       reg = <0x919c0 0x30>;
                        ranges;
 
                        muram@80000 {
                                #address-cells = <1>;
                                #size-cells = <1>;
-                               ranges = <0 80000 10000>;
+                               ranges = <0x0 0x80000 0x10000>;
 
                                data@0 {
                                        compatible = "fsl,cpm-muram-data";
-                                       reg = <0 2000 9000 1000>;
+                                       reg = <0x0 0x2000 0x9000 0x1000>;
                                };
                        };
 
                                compatible = "fsl,mpc8555-brg",
                                             "fsl,cpm2-brg",
                                             "fsl,cpm-brg";
-                               reg = <919f0 10 915f0 10>;
+                               reg = <0x919f0 0x10 0x915f0 0x10>;
                        };
 
                        cpmpic: pic@90c00 {
                                interrupt-controller;
                                #address-cells = <0>;
                                #interrupt-cells = <2>;
-                               interrupts = <2e 2>;
+                               interrupts = <46 2>;
                                interrupt-parent = <&mpic>;
-                               reg = <90c00 80>;
+                               reg = <0x90c00 0x80>;
                                compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
                        };
                };
 
        pci0: pci@e0008000 {
                cell-index = <0>;
-               interrupt-map-mask = <1f800 0 0 7>;
+               interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
                interrupt-map = <
 
                        /* IDSEL 0x10 */
-                       08000 0 0 1 &mpic 0 1
-                       08000 0 0 2 &mpic 1 1
-                       08000 0 0 3 &mpic 2 1
-                       08000 0 0 4 &mpic 3 1
+                       0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                        /* IDSEL 0x11 */
-                       08800 0 0 1 &mpic 0 1
-                       08800 0 0 2 &mpic 1 1
-                       08800 0 0 3 &mpic 2 1
-                       08800 0 0 4 &mpic 3 1
+                       0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                        /* IDSEL 0x12 (Slot 1) */
-                       09000 0 0 1 &mpic 0 1
-                       09000 0 0 2 &mpic 1 1
-                       09000 0 0 3 &mpic 2 1
-                       09000 0 0 4 &mpic 3 1
+                       0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
 
                        /* IDSEL 0x13 (Slot 2) */
-                       09800 0 0 1 &mpic 1 1
-                       09800 0 0 2 &mpic 2 1
-                       09800 0 0 3 &mpic 3 1
-                       09800 0 0 4 &mpic 0 1
+                       0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
+                       0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
+                       0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
+                       0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
 
                        /* IDSEL 0x14 (Slot 3) */
-                       0a000 0 0 1 &mpic 2 1
-                       0a000 0 0 2 &mpic 3 1
-                       0a000 0 0 3 &mpic 0 1
-                       0a000 0 0 4 &mpic 1 1
+                       0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
+                       0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
 
                        /* IDSEL 0x15 (Slot 4) */
-                       0a800 0 0 1 &mpic 3 1
-                       0a800 0 0 2 &mpic 0 1
-                       0a800 0 0 3 &mpic 1 1
-                       0a800 0 0 4 &mpic 2 1
+                       0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
+                       0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
+                       0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
+                       0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
 
                        /* Bus 1 (Tundra Bridge) */
                        /* IDSEL 0x12 (ISA bridge) */
-                       19000 0 0 1 &mpic 0 1
-                       19000 0 0 2 &mpic 1 1
-                       19000 0 0 3 &mpic 2 1
-                       19000 0 0 4 &mpic 3 1>;
+                       0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
                interrupt-parent = <&mpic>;
-               interrupts = <18 2>;
+               interrupts = <24 2>;
                bus-range = <0 0>;
-               ranges = <02000000 0 80000000 80000000 0 20000000
-                         01000000 0 00000000 e2000000 0 00100000>;
-               clock-frequency = <3f940aa>;
+               ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                         0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
+               clock-frequency = <66666666>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <e0008000 1000>;
+               reg = <0xe0008000 0x1000>;
                compatible = "fsl,mpc8540-pci";
                device_type = "pci";
 
                i8259@19000 {
                        interrupt-controller;
                        device_type = "interrupt-controller";
-                       reg = <19000 0 0 0 1>;
+                       reg = <0x19000 0x0 0x0 0x0 0x1>;
                        #address-cells = <0>;
                        #interrupt-cells = <2>;
                        compatible = "chrp,iic";
 
        pci1: pci@e0009000 {
                cell-index = <1>;
-               interrupt-map-mask = <f800 0 0 7>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
                        /* IDSEL 0x15 */
-                       a800 0 0 1 &mpic b 1
-                       a800 0 0 2 &mpic b 1
-                       a800 0 0 3 &mpic b 1
-                       a800 0 0 4 &mpic b 1>;
+                       0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+                       0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
+                       0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
+                       0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
                interrupt-parent = <&mpic>;
-               interrupts = <19 2>;
+               interrupts = <25 2>;
                bus-range = <0 0>;
-               ranges = <02000000 0 a0000000 a0000000 0 20000000
-                         01000000 0 00000000 e3000000 0 00100000>;
-               clock-frequency = <3f940aa>;
+               ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+                         0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
+               clock-frequency = <66666666>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <e0009000 1000>;
+               reg = <0xe0009000 0x1000>;
                compatible = "fsl,mpc8540-pci";
                device_type = "pci";
        };
index 639ce8a709a63b03fb05761a927ee52566b0a9e9..0cc16ab305d118879ad59dba5a144bc21a6af1c6 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * MPC8560 ADS Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
        model = "MPC8560ADS";
 
                PowerPC,8560@0 {
                        device_type = "cpu";
-                       reg = <0>;
-                       d-cache-line-size = <20>;       // 32 bytes
-                       i-cache-line-size = <20>;       // 32 bytes
-                       d-cache-size = <8000>;          // L1, 32K
-                       i-cache-size = <8000>;          // L1, 32K
-                       timebase-frequency = <04ead9a0>;
-                       bus-frequency = <13ab6680>;
-                       clock-frequency = <312c8040>;
+                       reg = <0x0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
+                       timebase-frequency = <82500000>;
+                       bus-frequency = <330000000>;
+                       clock-frequency = <825000000>;
                };
        };
 
        memory {
                device_type = "memory";
-               reg = <00000000 10000000>;
+               reg = <0x0 0x10000000>;
        };
 
        soc8560@e0000000 {
                #address-cells = <1>;
                #size-cells = <1>;
                device_type = "soc";
-               ranges = <0 e0000000 00100000>;
-               reg = <e0000000 00000200>;
-               bus-frequency = <13ab6680>;
+               ranges = <0x0 0xe0000000 0x100000>;
+               reg = <0xe0000000 0x200>;
+               bus-frequency = <330000000>;
 
                memory-controller@2000 {
                        compatible = "fsl,8540-memory-controller";
-                       reg = <2000 1000>;
+                       reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
-                       interrupts = <12 2>;
+                       interrupts = <18 2>;
                };
 
                l2-cache-controller@20000 {
                        compatible = "fsl,8540-l2-cache-controller";
-                       reg = <20000 1000>;
-                       cache-line-size = <20>; // 32 bytes
-                       cache-size = <40000>;   // L2, 256K
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x40000>; // L2, 256K
                        interrupt-parent = <&mpic>;
-                       interrupts = <10 2>;
+                       interrupts = <16 2>;
                };
 
                mdio@24520 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "fsl,gianfar-mdio";
-                       reg = <24520 20>;
+                       reg = <0x24520 0x20>;
 
                        phy0: ethernet-phy@0 {
                                interrupt-parent = <&mpic>;
                                interrupts = <5 1>;
-                               reg = <0>;
+                               reg = <0x0>;
                                device_type = "ethernet-phy";
                        };
                        phy1: ethernet-phy@1 {
                                interrupt-parent = <&mpic>;
                                interrupts = <5 1>;
-                               reg = <1>;
+                               reg = <0x1>;
                                device_type = "ethernet-phy";
                        };
                        phy2: ethernet-phy@2 {
                                interrupt-parent = <&mpic>;
                                interrupts = <7 1>;
-                               reg = <2>;
+                               reg = <0x2>;
                                device_type = "ethernet-phy";
                        };
                        phy3: ethernet-phy@3 {
                                interrupt-parent = <&mpic>;
                                interrupts = <7 1>;
-                               reg = <3>;
+                               reg = <0x3>;
                                device_type = "ethernet-phy";
                        };
                };
                        device_type = "network";
                        model = "TSEC";
                        compatible = "gianfar";
-                       reg = <24000 1000>;
+                       reg = <0x24000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <1d 2 1e 2 22 2>;
+                       interrupts = <29 2 30 2 34 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy0>;
                };
                        device_type = "network";
                        model = "TSEC";
                        compatible = "gianfar";
-                       reg = <25000 1000>;
+                       reg = <0x25000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <23 2 24 2 28 2>;
+                       interrupts = <35 2 36 2 40 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy1>;
                };
                        interrupt-controller;
                        #address-cells = <0>;
                        #interrupt-cells = <2>;
-                       reg = <40000 40000>;
+                       reg = <0x40000 0x40000>;
                        device_type = "open-pic";
                };
 
                        #address-cells = <1>;
                        #size-cells = <1>;
                        compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
-                       reg = <919c0 30>;
+                       reg = <0x919c0 0x30>;
                        ranges;
 
                        muram@80000 {
                                #address-cells = <1>;
                                #size-cells = <1>;
-                               ranges = <0 80000 10000>;
+                               ranges = <0x0 0x80000 0x10000>;
 
                                data@0 {
                                        compatible = "fsl,cpm-muram-data";
-                                       reg = <0 4000 9000 2000>;
+                                       reg = <0x0 0x4000 0x9000 0x2000>;
                                };
                        };
 
                                compatible = "fsl,mpc8560-brg",
                                             "fsl,cpm2-brg",
                                             "fsl,cpm-brg";
-                               reg = <919f0 10 915f0 10>;
-                               clock-frequency = <d#165000000>;
+                               reg = <0x919f0 0x10 0x915f0 0x10>;
+                               clock-frequency = <165000000>;
                        };
 
                        cpmpic: pic@90c00 {
                                interrupt-controller;
                                #address-cells = <0>;
                                #interrupt-cells = <2>;
-                               interrupts = <2e 2>;
+                               interrupts = <46 2>;
                                interrupt-parent = <&mpic>;
-                               reg = <90c00 80>;
+                               reg = <0x90c00 0x80>;
                                compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
                        };
 
                                device_type = "serial";
                                compatible = "fsl,mpc8560-scc-uart",
                                             "fsl,cpm2-scc-uart";
-                               reg = <91a00 20 88000 100>;
+                               reg = <0x91a00 0x20 0x88000 0x100>;
                                fsl,cpm-brg = <1>;
-                               fsl,cpm-command = <00800000>;
-                               current-speed = <1c200>;
-                               interrupts = <28 8>;
+                               fsl,cpm-command = <0x800000>;
+                               current-speed = <115200>;
+                               interrupts = <40 8>;
                                interrupt-parent = <&cpmpic>;
                        };
 
                                device_type = "serial";
                                compatible = "fsl,mpc8560-scc-uart",
                                             "fsl,cpm2-scc-uart";
-                               reg = <91a20 20 88100 100>;
+                               reg = <0x91a20 0x20 0x88100 0x100>;
                                fsl,cpm-brg = <2>;
-                               fsl,cpm-command = <04a00000>;
-                               current-speed = <1c200>;
-                               interrupts = <29 8>;
+                               fsl,cpm-command = <0x4a00000>;
+                               current-speed = <115200>;
+                               interrupts = <41 8>;
                                interrupt-parent = <&cpmpic>;
                        };
 
                                device_type = "network";
                                compatible = "fsl,mpc8560-fcc-enet",
                                             "fsl,cpm2-fcc-enet";
-                               reg = <91320 20 88500 100 913b0 1>;
+                               reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
                                local-mac-address = [ 00 00 00 00 00 00 ];
-                               fsl,cpm-command = <16200300>;
-                               interrupts = <21 8>;
+                               fsl,cpm-command = <0x16200300>;
+                               interrupts = <33 8>;
                                interrupt-parent = <&cpmpic>;
                                phy-handle = <&phy2>;
                        };
                                device_type = "network";
                                compatible = "fsl,mpc8560-fcc-enet",
                                             "fsl,cpm2-fcc-enet";
-                               reg = <91340 20 88600 100 913d0 1>;
+                               reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
                                local-mac-address = [ 00 00 00 00 00 00 ];
-                               fsl,cpm-command = <1a400300>;
-                               interrupts = <22 8>;
+                               fsl,cpm-command = <0x1a400300>;
+                               interrupts = <34 8>;
                                interrupt-parent = <&cpmpic>;
                                phy-handle = <&phy3>;
                        };
                #address-cells = <3>;
                compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
                device_type = "pci";
-               reg = <e0008000 1000>;
-               clock-frequency = <3f940aa>;
-               interrupt-map-mask = <f800 0 0 7>;
+               reg = <0xe0008000 0x1000>;
+               clock-frequency = <66666666>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
                                /* IDSEL 0x2 */
-                                1000 0 0 1 &mpic 1 1
-                                1000 0 0 2 &mpic 2 1
-                                1000 0 0 3 &mpic 3 1
-                                1000 0 0 4 &mpic 4 1
+                                0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
+                                0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
+                                0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
+                                0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
 
                                /* IDSEL 0x3 */
-                                1800 0 0 1 &mpic 4 1
-                                1800 0 0 2 &mpic 1 1
-                                1800 0 0 3 &mpic 2 1
-                                1800 0 0 4 &mpic 3 1
+                                0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
+                                0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
+                                0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
+                                0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                                /* IDSEL 0x4 */
-                                2000 0 0 1 &mpic 3 1
-                                2000 0 0 2 &mpic 4 1
-                                2000 0 0 3 &mpic 1 1
-                                2000 0 0 4 &mpic 2 1
+                                0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
+                                0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
+                                0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
+                                0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
 
                                /* IDSEL 0x5  */
-                                2800 0 0 1 &mpic 2 1
-                                2800 0 0 2 &mpic 3 1
-                                2800 0 0 3 &mpic 4 1
-                                2800 0 0 4 &mpic 1 1
+                                0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
+                                0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
+                                0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
+                                0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
 
                                /* IDSEL 12 */
-                                6000 0 0 1 &mpic 1 1
-                                6000 0 0 2 &mpic 2 1
-                                6000 0 0 3 &mpic 3 1
-                                6000 0 0 4 &mpic 4 1
+                                0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
+                                0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
+                                0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
+                                0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
 
                                /* IDSEL 13 */
-                                6800 0 0 1 &mpic 4 1
-                                6800 0 0 2 &mpic 1 1
-                                6800 0 0 3 &mpic 2 1
-                                6800 0 0 4 &mpic 3 1
+                                0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
+                                0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
+                                0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
+                                0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                                /* IDSEL 14*/
-                                7000 0 0 1 &mpic 3 1
-                                7000 0 0 2 &mpic 4 1
-                                7000 0 0 3 &mpic 1 1
-                                7000 0 0 4 &mpic 2 1
+                                0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
+                                0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
+                                0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
+                                0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
 
                                /* IDSEL 15 */
-                                7800 0 0 1 &mpic 2 1
-                                7800 0 0 2 &mpic 3 1
-                                7800 0 0 3 &mpic 4 1
-                                7800 0 0 4 &mpic 1 1
+                                0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
+                                0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
+                                0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
+                                0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
 
                                /* IDSEL 18 */
-                                9000 0 0 1 &mpic 1 1
-                                9000 0 0 2 &mpic 2 1
-                                9000 0 0 3 &mpic 3 1
-                                9000 0 0 4 &mpic 4 1
+                                0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
+                                0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
+                                0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
+                                0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 
                                /* IDSEL 19 */
-                                9800 0 0 1 &mpic 4 1
-                                9800 0 0 2 &mpic 1 1
-                                9800 0 0 3 &mpic 2 1
-                                9800 0 0 4 &mpic 3 1
+                                0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
+                                0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
+                                0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
+                                0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
 
                                /* IDSEL 20 */
-                                a000 0 0 1 &mpic 3 1
-                                a000 0 0 2 &mpic 4 1
-                                a000 0 0 3 &mpic 1 1
-                                a000 0 0 4 &mpic 2 1
+                                0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
+                                0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
+                                0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
+                                0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
 
                                /* IDSEL 21 */
-                                a800 0 0 1 &mpic 2 1
-                                a800 0 0 2 &mpic 3 1
-                                a800 0 0 3 &mpic 4 1
-                                a800 0 0 4 &mpic 1 1>;
+                                0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
+                                0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
+                                0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
+                                0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
 
                interrupt-parent = <&mpic>;
-               interrupts = <18 2>;
+               interrupts = <24 2>;
                bus-range = <0 0>;
-               ranges = <02000000 0 80000000 80000000 0 20000000
-                         01000000 0 00000000 e2000000 0 01000000>;
+               ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                         0x1000000 0x0 0x0 0xe2000000 0x0 0x1000000>;
        };
 };
index df4b5e89d7e456b94cc2f562d68d7aadeee8e860..3e6739fc0aa27f46431b903bcec67127f215a519 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * MPC8568E MDS Device Tree Source
  *
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 /*
 /memreserve/   00000000 1000000;
 
                PowerPC,8568@0 {
                        device_type = "cpu";
-                       reg = <0>;
-                       d-cache-line-size = <20>;       // 32 bytes
-                       i-cache-line-size = <20>;       // 32 bytes
-                       d-cache-size = <8000>;          // L1, 32K
-                       i-cache-size = <8000>;          // L1, 32K
+                       reg = <0x0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
 
        memory {
                device_type = "memory";
-               reg = <00000000 10000000>;
+               reg = <0x0 0x10000000>;
        };
 
        bcsr@f8000000 {
                device_type = "board-control";
-               reg = <f8000000 8000>;
+               reg = <0xf8000000 0x8000>;
        };
 
        soc8568@e0000000 {
                #address-cells = <1>;
                #size-cells = <1>;
                device_type = "soc";
-               ranges = <0 e0000000 00100000>;
-               reg = <e0000000 00001000>;
+               ranges = <0x0 0xe0000000 0x100000>;
+               reg = <0xe0000000 0x1000>;
                bus-frequency = <0>;
 
                memory-controller@2000 {
                        compatible = "fsl,8568-memory-controller";
-                       reg = <2000 1000>;
+                       reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
-                       interrupts = <12 2>;
+                       interrupts = <18 2>;
                };
 
                l2-cache-controller@20000 {
                        compatible = "fsl,8568-l2-cache-controller";
-                       reg = <20000 1000>;
-                       cache-line-size = <20>; // 32 bytes
-                       cache-size = <80000>;   // L2, 512K
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x80000>; // L2, 512K
                        interrupt-parent = <&mpic>;
-                       interrupts = <10 2>;
+                       interrupts = <16 2>;
                };
 
                i2c@3000 {
                        #size-cells = <0>;
                        cell-index = <0>;
                        compatible = "fsl-i2c";
-                       reg = <3000 100>;
-                       interrupts = <2b 2>;
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
                        interrupt-parent = <&mpic>;
                        dfsrr;
 
                        rtc@68 {
                                compatible = "dallas,ds1374";
-                               reg = <68>;
+                               reg = <0x68>;
                        };
                };
 
                        #size-cells = <0>;
                        cell-index = <1>;
                        compatible = "fsl-i2c";
-                       reg = <3100 100>;
-                       interrupts = <2b 2>;
+                       reg = <0x3100 0x100>;
+                       interrupts = <43 2>;
                        interrupt-parent = <&mpic>;
                        dfsrr;
                };
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "fsl,gianfar-mdio";
-                       reg = <24520 20>;
+                       reg = <0x24520 0x20>;
 
                        phy0: ethernet-phy@7 {
                                interrupt-parent = <&mpic>;
                                interrupts = <1 1>;
-                               reg = <7>;
+                               reg = <0x7>;
                                device_type = "ethernet-phy";
                        };
                        phy1: ethernet-phy@1 {
                                interrupt-parent = <&mpic>;
                                interrupts = <2 1>;
-                               reg = <1>;
+                               reg = <0x1>;
                                device_type = "ethernet-phy";
                        };
                        phy2: ethernet-phy@2 {
                                interrupt-parent = <&mpic>;
                                interrupts = <1 1>;
-                               reg = <2>;
+                               reg = <0x2>;
                                device_type = "ethernet-phy";
                        };
                        phy3: ethernet-phy@3 {
                                interrupt-parent = <&mpic>;
                                interrupts = <2 1>;
-                               reg = <3>;
+                               reg = <0x3>;
                                device_type = "ethernet-phy";
                        };
                };
                        device_type = "network";
                        model = "eTSEC";
                        compatible = "gianfar";
-                       reg = <24000 1000>;
+                       reg = <0x24000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <1d 2 1e 2 22 2>;
+                       interrupts = <29 2 30 2 34 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy2>;
                };
                        device_type = "network";
                        model = "eTSEC";
                        compatible = "gianfar";
-                       reg = <25000 1000>;
+                       reg = <0x25000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <23 2 24 2 28 2>;
+                       interrupts = <35 2 36 2 40 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy3>;
                };
                        cell-index = <0>;
                        device_type = "serial";
                        compatible = "ns16550";
-                       reg = <4500 100>;
+                       reg = <0x4500 0x100>;
                        clock-frequency = <0>;
-                       interrupts = <2a 2>;
+                       interrupts = <42 2>;
                        interrupt-parent = <&mpic>;
                };
 
                global-utilities@e0000 {        //global utilities block
                        compatible = "fsl,mpc8548-guts";
-                       reg = <e0000 1000>;
+                       reg = <0xe0000 0x1000>;
                        fsl,has-rstcr;
                };
 
                        cell-index = <1>;
                        device_type = "serial";
                        compatible = "ns16550";
-                       reg = <4600 100>;
+                       reg = <0x4600 0x100>;
                        clock-frequency = <0>;
-                       interrupts = <2a 2>;
+                       interrupts = <42 2>;
                        interrupt-parent = <&mpic>;
                };
 
                        device_type = "crypto";
                        model = "SEC2";
                        compatible = "talitos";
-                       reg = <30000 f000>;
-                       interrupts = <2d 2>;
+                       reg = <0x30000 0xf000>;
+                       interrupts = <45 2>;
                        interrupt-parent = <&mpic>;
                        num-channels = <4>;
-                       channel-fifo-len = <18>;
-                       exec-units-mask = <000000fe>;
-                       descriptor-types-mask = <012b0ebf>;
+                       channel-fifo-len = <24>;
+                       exec-units-mask = <0xfe>;
+                       descriptor-types-mask = <0x12b0ebf>;
                };
 
                mpic: pic@40000 {
                        interrupt-controller;
                        #address-cells = <0>;
                        #interrupt-cells = <2>;
-                       reg = <40000 40000>;
+                       reg = <0x40000 0x40000>;
                        compatible = "chrp,open-pic";
                        device_type = "open-pic";
                         big-endian;
                };
 
                par_io@e0100 {
-                       reg = <e0100 100>;
+                       reg = <0xe0100 0x100>;
                        device_type = "par_io";
                        num-ports = <7>;
 
                        pio1: ucc_pin@01 {
                                pio-map = <
                        /* port  pin  dir  open_drain  assignment  has_irq */
-                                       4  0a  1  0  2  0       /* TxD0 */
-                                       4  09  1  0  2  0       /* TxD1 */
-                                       4  08  1  0  2  0       /* TxD2 */
-                                       4  07  1  0  2  0       /* TxD3 */
-                                       4  17  1  0  2  0       /* TxD4 */
-                                       4  16  1  0  2  0       /* TxD5 */
-                                       4  15  1  0  2  0       /* TxD6 */
-                                       4  14  1  0  2  0       /* TxD7 */
-                                       4  0f  2  0  2  0       /* RxD0 */
-                                       4  0e  2  0  2  0       /* RxD1 */
-                                       4  0d  2  0  2  0       /* RxD2 */
-                                       4  0c  2  0  2  0       /* RxD3 */
-                                       4  1d  2  0  2  0       /* RxD4 */
-                                       4  1c  2  0  2  0       /* RxD5 */
-                                       4  1b  2  0  2  0       /* RxD6 */
-                                       4  1a  2  0  2  0       /* RxD7 */
-                                       4  0b  1  0  2  0       /* TX_EN */
-                                       4  18  1  0  2  0       /* TX_ER */
-                                       4  10  2  0  2  0       /* RX_DV */
-                                       4  1e  2  0  2  0       /* RX_ER */
-                                       4  11  2  0  2  0       /* RX_CLK */
-                                       4  13  1  0  2  0       /* GTX_CLK */
-                                       1  1f  2  0  3  0>;     /* GTX125 */
+                                       0x4  0xa  0x1  0x0  0x2  0x0    /* TxD0 */
+                                       0x4  0x9  0x1  0x0  0x2  0x0    /* TxD1 */
+                                       0x4  0x8  0x1  0x0  0x2  0x0    /* TxD2 */
+                                       0x4  0x7  0x1  0x0  0x2  0x0    /* TxD3 */
+                                       0x4  0x17  0x1  0x0  0x2  0x0   /* TxD4 */
+                                       0x4  0x16  0x1  0x0  0x2  0x0   /* TxD5 */
+                                       0x4  0x15  0x1  0x0  0x2  0x0   /* TxD6 */
+                                       0x4  0x14  0x1  0x0  0x2  0x0   /* TxD7 */
+                                       0x4  0xf  0x2  0x0  0x2  0x0    /* RxD0 */
+                                       0x4  0xe  0x2  0x0  0x2  0x0    /* RxD1 */
+                                       0x4  0xd  0x2  0x0  0x2  0x0    /* RxD2 */
+                                       0x4  0xc  0x2  0x0  0x2  0x0    /* RxD3 */
+                                       0x4  0x1d  0x2  0x0  0x2  0x0   /* RxD4 */
+                                       0x4  0x1c  0x2  0x0  0x2  0x0   /* RxD5 */
+                                       0x4  0x1b  0x2  0x0  0x2  0x0   /* RxD6 */
+                                       0x4  0x1a  0x2  0x0  0x2  0x0   /* RxD7 */
+                                       0x4  0xb  0x1  0x0  0x2  0x0    /* TX_EN */
+                                       0x4  0x18  0x1  0x0  0x2  0x0   /* TX_ER */
+                                       0x4  0x10  0x2  0x0  0x2  0x0   /* RX_DV */
+                                       0x4  0x1e  0x2  0x0  0x2  0x0   /* RX_ER */
+                                       0x4  0x11  0x2  0x0  0x2  0x0   /* RX_CLK */
+                                       0x4  0x13  0x1  0x0  0x2  0x0   /* GTX_CLK */
+                                       0x1  0x1f  0x2  0x0  0x3  0x0>; /* GTX125 */
                        };
 
                        pio2: ucc_pin@02 {
                                pio-map = <
                        /* port  pin  dir  open_drain  assignment  has_irq */
-                                       5  0a 1  0  2  0   /* TxD0 */
-                                       5  09 1  0  2  0   /* TxD1 */
-                                       5  08 1  0  2  0   /* TxD2 */
-                                       5  07 1  0  2  0   /* TxD3 */
-                                       5  17 1  0  2  0   /* TxD4 */
-                                       5  16 1  0  2  0   /* TxD5 */
-                                       5  15 1  0  2  0   /* TxD6 */
-                                       5  14 1  0  2  0   /* TxD7 */
-                                       5  0f 2  0  2  0   /* RxD0 */
-                                       5  0e 2  0  2  0   /* RxD1 */
-                                       5  0d 2  0  2  0   /* RxD2 */
-                                       5  0c 2  0  2  0   /* RxD3 */
-                                       5  1d 2  0  2  0   /* RxD4 */
-                                       5  1c 2  0  2  0   /* RxD5 */
-                                       5  1b 2  0  2  0   /* RxD6 */
-                                       5  1a 2  0  2  0   /* RxD7 */
-                                       5  0b 1  0  2  0   /* TX_EN */
-                                       5  18 1  0  2  0   /* TX_ER */
-                                       5  10 2  0  2  0   /* RX_DV */
-                                       5  1e 2  0  2  0   /* RX_ER */
-                                       5  11 2  0  2  0   /* RX_CLK */
-                                       5  13 1  0  2  0   /* GTX_CLK */
-                                       1  1f 2  0  3  0   /* GTX125 */
-                                       4  06 3  0  2  0   /* MDIO */
-                                       4  05 1  0  2  0>; /* MDC */
+                                       0x5  0xa 0x1  0x0  0x2  0x0   /* TxD0 */
+                                       0x5  0x9 0x1  0x0  0x2  0x0   /* TxD1 */
+                                       0x5  0x8 0x1  0x0  0x2  0x0   /* TxD2 */
+                                       0x5  0x7 0x1  0x0  0x2  0x0   /* TxD3 */
+                                       0x5  0x17 0x1  0x0  0x2  0x0   /* TxD4 */
+                                       0x5  0x16 0x1  0x0  0x2  0x0   /* TxD5 */
+                                       0x5  0x15 0x1  0x0  0x2  0x0   /* TxD6 */
+                                       0x5  0x14 0x1  0x0  0x2  0x0   /* TxD7 */
+                                       0x5  0xf 0x2  0x0  0x2  0x0   /* RxD0 */
+                                       0x5  0xe 0x2  0x0  0x2  0x0   /* RxD1 */
+                                       0x5  0xd 0x2  0x0  0x2  0x0   /* RxD2 */
+                                       0x5  0xc 0x2  0x0  0x2  0x0   /* RxD3 */
+                                       0x5  0x1d 0x2  0x0  0x2  0x0   /* RxD4 */
+                                       0x5  0x1c 0x2  0x0  0x2  0x0   /* RxD5 */
+                                       0x5  0x1b 0x2  0x0  0x2  0x0   /* RxD6 */
+                                       0x5  0x1a 0x2  0x0  0x2  0x0   /* RxD7 */
+                                       0x5  0xb 0x1  0x0  0x2  0x0   /* TX_EN */
+                                       0x5  0x18 0x1  0x0  0x2  0x0   /* TX_ER */
+                                       0x5  0x10 0x2  0x0  0x2  0x0   /* RX_DV */
+                                       0x5  0x1e 0x2  0x0  0x2  0x0   /* RX_ER */
+                                       0x5  0x11 0x2  0x0  0x2  0x0   /* RX_CLK */
+                                       0x5  0x13 0x1  0x0  0x2  0x0   /* GTX_CLK */
+                                       0x1  0x1f 0x2  0x0  0x3  0x0   /* GTX125 */
+                                       0x4  0x6 0x3  0x0  0x2  0x0   /* MDIO */
+                                       0x4  0x5 0x1  0x0  0x2  0x0>; /* MDC */
                        };
                };
        };
                #size-cells = <1>;
                device_type = "qe";
                compatible = "fsl,qe";
-               ranges = <0 e0080000 00040000>;
-               reg = <e0080000 480>;
+               ranges = <0x0 0xe0080000 0x40000>;
+               reg = <0xe0080000 0x480>;
                brg-frequency = <0>;
-               bus-frequency = <179A7B00>;
+               bus-frequency = <396000000>;
 
                muram@10000 {
                        #address-cells = <1>;
                        #size-cells = <1>;
                        compatible = "fsl,qe-muram", "fsl,cpm-muram";
-                       ranges = <0 00010000 0000c000>;
+                       ranges = <0x0 0x10000 0xc000>;
 
                        data-only@0 {
                                compatible = "fsl,qe-muram-data",
                                             "fsl,cpm-muram-data";
-                               reg = <0 c000>;
+                               reg = <0x0 0xc000>;
                        };
                };
 
                spi@4c0 {
                        cell-index = <0>;
                        compatible = "fsl,spi";
-                       reg = <4c0 40>;
+                       reg = <0x4c0 0x40>;
                        interrupts = <2>;
                        interrupt-parent = <&qeic>;
                        mode = "cpu";
                spi@500 {
                        cell-index = <1>;
                        compatible = "fsl,spi";
-                       reg = <500 40>;
+                       reg = <0x500 0x40>;
                        interrupts = <1>;
                        interrupt-parent = <&qeic>;
                        mode = "cpu";
                        device_type = "network";
                        compatible = "ucc_geth";
                        cell-index = <1>;
-                       reg = <2000 200>;
-                       interrupts = <20>;
+                       reg = <0x2000 0x200>;
+                       interrupts = <32>;
                        interrupt-parent = <&qeic>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
                        rx-clock-name = "none";
                        device_type = "network";
                        compatible = "ucc_geth";
                        cell-index = <2>;
-                       reg = <3000 200>;
-                       interrupts = <21>;
+                       reg = <0x3000 0x200>;
+                       interrupts = <33>;
                        interrupt-parent = <&qeic>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
                        rx-clock-name = "none";
                mdio@2120 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       reg = <2120 18>;
+                       reg = <0x2120 0x18>;
                        compatible = "fsl,ucc-mdio";
 
                        /* These are the same PHYs as on
                        qe_phy0: ethernet-phy@07 {
                                interrupt-parent = <&mpic>;
                                interrupts = <1 1>;
-                               reg = <7>;
+                               reg = <0x7>;
                                device_type = "ethernet-phy";
                        };
                        qe_phy1: ethernet-phy@01 {
                                interrupt-parent = <&mpic>;
                                interrupts = <2 1>;
-                               reg = <1>;
+                               reg = <0x1>;
                                device_type = "ethernet-phy";
                        };
                        qe_phy2: ethernet-phy@02 {
                                interrupt-parent = <&mpic>;
                                interrupts = <1 1>;
-                               reg = <2>;
+                               reg = <0x2>;
                                device_type = "ethernet-phy";
                        };
                        qe_phy3: ethernet-phy@03 {
                                interrupt-parent = <&mpic>;
                                interrupts = <2 1>;
-                               reg = <3>;
+                               reg = <0x3>;
                                device_type = "ethernet-phy";
                        };
                };
                        compatible = "fsl,qe-ic";
                        #address-cells = <0>;
                        #interrupt-cells = <1>;
-                       reg = <80 80>;
+                       reg = <0x80 0x80>;
                        big-endian;
-                       interrupts = <2e 2 2e 2>; //high:30 low:30
+                       interrupts = <46 2 46 2>; //high:30 low:30
                        interrupt-parent = <&mpic>;
                };
 
 
        pci0: pci@e0008000 {
                cell-index = <0>;
-               interrupt-map-mask = <f800 0 0 7>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x12 AD18 */
-                       9000 0 0 1 &mpic 5 1
-                       9000 0 0 2 &mpic 6 1
-                       9000 0 0 3 &mpic 7 1
-                       9000 0 0 4 &mpic 4 1
+                       0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
+                       0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
+                       0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
+                       0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 
                        /* IDSEL 0x13 AD19 */
-                       9800 0 0 1 &mpic 6 1
-                       9800 0 0 2 &mpic 7 1
-                       9800 0 0 3 &mpic 4 1
-                       9800 0 0 4 &mpic 5 1>;
+                       0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
+                       0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
+                       0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
+                       0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
 
                interrupt-parent = <&mpic>;
-               interrupts = <18 2>;
-               bus-range = <0 ff>;
-               ranges = <02000000 0 80000000 80000000 0 20000000
-                         01000000 0 00000000 e2000000 0 00800000>;
-               clock-frequency = <3f940aa>;
+               interrupts = <24 2>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                         0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
+               clock-frequency = <66666666>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <e0008000 1000>;
+               reg = <0xe0008000 0x1000>;
                compatible = "fsl,mpc8540-pci";
                device_type = "pci";
        };
        /* PCI Express */
        pci1: pcie@e000a000 {
                cell-index = <2>;
-               interrupt-map-mask = <f800 0 0 7>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
                        /* IDSEL 0x0 (PEX) */
-                       00000 0 0 1 &mpic 0 1
-                       00000 0 0 2 &mpic 1 1
-                       00000 0 0 3 &mpic 2 1
-                       00000 0 0 4 &mpic 3 1>;
+                       00000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       00000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       00000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 
                interrupt-parent = <&mpic>;
-               interrupts = <1a 2>;
-               bus-range = <0 ff>;
-               ranges = <02000000 0 a0000000 a0000000 0 10000000
-                         01000000 0 00000000 e2800000 0 00800000>;
-               clock-frequency = <1fca055>;
+               interrupts = <26 2>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
+                         0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
+               clock-frequency = <33333333>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <e000a000 1000>;
+               reg = <0xe000a000 0x1000>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                pcie@0 {
-                       reg = <0 0 0 0 0>;
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                       ranges = <02000000 0 a0000000
-                                 02000000 0 a0000000
-                                 0 10000000
+                       ranges = <0x2000000 0x0 0xa0000000
+                                 0x2000000 0x0 0xa0000000
+                                 0x0 0x10000000
 
-                                 01000000 0 00000000
-                                 01000000 0 00000000
-                                 0 00800000>;
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x800000>;
                };
        };
 };
index db37214aee37a0851bbacffe70f64e565608c3f9..66f27ab613a28eb89f893c98283af7aef9ad2c25 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * MPC8572 DS Device Tree Source
  *
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 / {
        model = "fsl,MPC8572DS";
        compatible = "fsl,MPC8572DS";
 
                PowerPC,8572@0 {
                        device_type = "cpu";
-                       reg = <0>;
-                       d-cache-line-size = <20>;       // 32 bytes
-                       i-cache-line-size = <20>;       // 32 bytes
-                       d-cache-size = <8000>;          // L1, 32K
-                       i-cache-size = <8000>;          // L1, 32K
+                       reg = <0x0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
 
                PowerPC,8572@1 {
                        device_type = "cpu";
-                       reg = <1>;
-                       d-cache-line-size = <20>;       // 32 bytes
-                       i-cache-line-size = <20>;       // 32 bytes
-                       d-cache-size = <8000>;          // L1, 32K
-                       i-cache-size = <8000>;          // L1, 32K
+                       reg = <0x1>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
 
        memory {
                device_type = "memory";
-               reg = <00000000 00000000>;      // Filled by U-Boot
+               reg = <0x0 0x0>;        // Filled by U-Boot
        };
 
        soc8572@ffe00000 {
                #address-cells = <1>;
                #size-cells = <1>;
                device_type = "soc";
-               ranges = <00000000 ffe00000 00100000>;
-               reg = <ffe00000 00001000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
+               ranges = <0x0 0xffe00000 0x100000>;
+               reg = <0xffe00000 0x1000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
                bus-frequency = <0>;            // Filled out by uboot.
 
                memory-controller@2000 {
                        compatible = "fsl,mpc8572-memory-controller";
-                       reg = <2000 1000>;
+                       reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
-                       interrupts = <12 2>;
+                       interrupts = <18 2>;
                };
 
                memory-controller@6000 {
                        compatible = "fsl,mpc8572-memory-controller";
-                       reg = <6000 1000>;
+                       reg = <0x6000 0x1000>;
                        interrupt-parent = <&mpic>;
-                       interrupts = <12 2>;
+                       interrupts = <18 2>;
                };
 
                l2-cache-controller@20000 {
                        compatible = "fsl,mpc8572-l2-cache-controller";
-                       reg = <20000 1000>;
-                       cache-line-size = <20>; // 32 bytes
-                       cache-size = <80000>;   // L2, 512K
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x80000>; // L2, 512K
                        interrupt-parent = <&mpic>;
-                       interrupts = <10 2>;
+                       interrupts = <16 2>;
                };
 
                i2c@3000 {
@@ -97,8 +98,8 @@
                        #size-cells = <0>;
                        cell-index = <0>;
                        compatible = "fsl-i2c";
-                       reg = <3000 100>;
-                       interrupts = <2b 2>;
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
                        interrupt-parent = <&mpic>;
                        dfsrr;
                };
                        #size-cells = <0>;
                        cell-index = <1>;
                        compatible = "fsl-i2c";
-                       reg = <3100 100>;
-                       interrupts = <2b 2>;
+                       reg = <0x3100 0x100>;
+                       interrupts = <43 2>;
                        interrupt-parent = <&mpic>;
                        dfsrr;
                };
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "fsl,gianfar-mdio";
-                       reg = <24520 20>;
+                       reg = <0x24520 0x20>;
 
                        phy0: ethernet-phy@0 {
                                interrupt-parent = <&mpic>;
-                               interrupts = <a 1>;
-                               reg = <0>;
+                               interrupts = <10 1>;
+                               reg = <0x0>;
                        };
                        phy1: ethernet-phy@1 {
                                interrupt-parent = <&mpic>;
-                               interrupts = <a 1>;
-                               reg = <1>;
+                               interrupts = <10 1>;
+                               reg = <0x1>;
                        };
                        phy2: ethernet-phy@2 {
                                interrupt-parent = <&mpic>;
-                               interrupts = <a 1>;
-                               reg = <2>;
+                               interrupts = <10 1>;
+                               reg = <0x2>;
                        };
                        phy3: ethernet-phy@3 {
                                interrupt-parent = <&mpic>;
-                               interrupts = <a 1>;
-                               reg = <3>;
+                               interrupts = <10 1>;
+                               reg = <0x3>;
                        };
                };
 
                        device_type = "network";
                        model = "eTSEC";
                        compatible = "gianfar";
-                       reg = <24000 1000>;
+                       reg = <0x24000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <1d 2 1e 2 22 2>;
+                       interrupts = <29 2 30 2 34 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy0>;
                        phy-connection-type = "rgmii-id";
                        device_type = "network";
                        model = "eTSEC";
                        compatible = "gianfar";
-                       reg = <25000 1000>;
+                       reg = <0x25000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <23 2 24 2 28 2>;
+                       interrupts = <35 2 36 2 40 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy1>;
                        phy-connection-type = "rgmii-id";
                        device_type = "network";
                        model = "eTSEC";
                        compatible = "gianfar";
-                       reg = <26000 1000>;
+                       reg = <0x26000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <1f 2 20 2 21 2>;
+                       interrupts = <31 2 32 2 33 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy2>;
                        phy-connection-type = "rgmii-id";
                        device_type = "network";
                        model = "eTSEC";
                        compatible = "gianfar";
-                       reg = <27000 1000>;
+                       reg = <0x27000 0x1000>;
                        local-mac-address = [ 00 00 00 00 00 00 ];
-                       interrupts = <25 2 26 2 27 2>;
+                       interrupts = <37 2 38 2 39 2>;
                        interrupt-parent = <&mpic>;
                        phy-handle = <&phy3>;
                        phy-connection-type = "rgmii-id";
                        cell-index = <0>;
                        device_type = "serial";
                        compatible = "ns16550";
-                       reg = <4500 100>;
+                       reg = <0x4500 0x100>;
                        clock-frequency = <0>;
-                       interrupts = <2a 2>;
+                       interrupts = <42 2>;
                        interrupt-parent = <&mpic>;
                };
 
                        cell-index = <1>;
                        device_type = "serial";
                        compatible = "ns16550";
-                       reg = <4600 100>;
+                       reg = <0x4600 0x100>;
                        clock-frequency = <0>;
-                       interrupts = <2a 2>;
+                       interrupts = <42 2>;
                        interrupt-parent = <&mpic>;
                };
 
                global-utilities@e0000 {        //global utilities block
                        compatible = "fsl,mpc8572-guts";
-                       reg = <e0000 1000>;
+                       reg = <0xe0000 0x1000>;
                        fsl,has-rstcr;
                };
 
                        interrupt-controller;
                        #address-cells = <0>;
                        #interrupt-cells = <2>;
-                       reg = <40000 40000>;
+                       reg = <0x40000 0x40000>;
                        compatible = "chrp,open-pic";
                        device_type = "open-pic";
                        big-endian;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <ffe08000 1000>;
-               bus-range = <0 ff>;
-               ranges = <02000000 0 80000000 80000000 0 20000000
-                         01000000 0 00000000 ffc00000 0 00010000>;
-               clock-frequency = <1fca055>;
+               reg = <0xffe08000 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                         0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
+               clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
-               interrupts = <18 2>;
-               interrupt-map-mask = <ff00 0 0 7>;
+               interrupts = <24 2>;
+               interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x11 func 0 - PCI slot 1 */
-                       8800 0 0 1 &mpic 2 1
-                       8800 0 0 2 &mpic 3 1
-                       8800 0 0 3 &mpic 4 1
-                       8800 0 0 4 &mpic 1 1
+                       0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
+                       0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
 
                        /* IDSEL 0x11 func 1 - PCI slot 1 */
-                       8900 0 0 1 &mpic 2 1
-                       8900 0 0 2 &mpic 3 1
-                       8900 0 0 3 &mpic 4 1
-                       8900 0 0 4 &mpic 1 1
+                       0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
+                       0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
 
                        /* IDSEL 0x11 func 2 - PCI slot 1 */
-                       8a00 0 0 1 &mpic 2 1
-                       8a00 0 0 2 &mpic 3 1
-                       8a00 0 0 3 &mpic 4 1
-                       8a00 0 0 4 &mpic 1 1
+                       0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
+                       0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
 
                        /* IDSEL 0x11 func 3 - PCI slot 1 */
-                       8b00 0 0 1 &mpic 2 1
-                       8b00 0 0 2 &mpic 3 1
-                       8b00 0 0 3 &mpic 4 1
-                       8b00 0 0 4 &mpic 1 1
+                       0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
+                       0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
 
                        /* IDSEL 0x11 func 4 - PCI slot 1 */
-                       8c00 0 0 1 &mpic 2 1
-                       8c00 0 0 2 &mpic 3 1
-                       8c00 0 0 3 &mpic 4 1
-                       8c00 0 0 4 &mpic 1 1
+                       0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
+                       0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
 
                        /* IDSEL 0x11 func 5 - PCI slot 1 */
-                       8d00 0 0 1 &mpic 2 1
-                       8d00 0 0 2 &mpic 3 1
-                       8d00 0 0 3 &mpic 4 1
-                       8d00 0 0 4 &mpic 1 1
+                       0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
+                       0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
 
                        /* IDSEL 0x11 func 6 - PCI slot 1 */
-                       8e00 0 0 1 &mpic 2 1
-                       8e00 0 0 2 &mpic 3 1
-                       8e00 0 0 3 &mpic 4 1
-                       8e00 0 0 4 &mpic 1 1
+                       0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
+                       0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
 
                        /* IDSEL 0x11 func 7 - PCI slot 1 */
-                       8f00 0 0 1 &mpic 2 1
-                       8f00 0 0 2 &mpic 3 1
-                       8f00 0 0 3 &mpic 4 1
-                       8f00 0 0 4 &mpic 1 1
+                       0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
+                       0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
+                       0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
+                       0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
 
                        /* IDSEL 0x12 func 0 - PCI slot 2 */
-                       9000 0 0 1 &mpic 3 1
-                       9000 0 0 2 &mpic 4 1
-                       9000 0 0 3 &mpic 1 1
-                       9000 0 0 4 &mpic 2 1
+                       0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
+                       0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
+                       0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
+                       0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
 
                        /* IDSEL 0x12 func 1 - PCI slot 2 */
-                       9100 0 0 1 &mpic 3 1
-                       9100 0 0 2 &mpic 4 1
-                       9100 0 0 3 &mpic 1 1
-                       9100 0 0 4 &mpic 2 1
+                       0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
+                       0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
+                       0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
+                       0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
 
                        /* IDSEL 0x12 func 2 - PCI slot 2 */
-                       9200 0 0 1 &mpic 3 1
-                       9200 0 0 2 &mpic 4 1
-                       9200 0 0 3 &mpic 1 1
-                       9200 0 0 4 &mpic 2 1
+                       0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
+                       0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
+                       0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
+                       0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
 
                        /* IDSEL 0x12 func 3 - PCI slot 2 */
-                       9300 0 0 1 &mpic 3 1
-                       9300 0 0 2 &mpic 4 1
-                       9300 0 0 3 &mpic 1 1
-                       9300 0 0 4 &mpic 2 1
+                       0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
+                       0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
+                       0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
+                       0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
 
                        /* IDSEL 0x12 func 4 - PCI slot 2 */
-                       9400 0 0 1 &mpic 3 1
-                       9400 0 0 2 &mpic 4 1
-                       9400 0 0 3 &mpic 1 1
-                       9400 0 0 4 &mpic 2 1
+                       0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
+                       0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
+                       0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
+                       0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
 
                        /* IDSEL 0x12 func 5 - PCI slot 2 */
-                       9500 0 0 1 &mpic 3 1
-                       9500 0 0 2 &mpic 4 1
-                       9500 0 0 3 &mpic 1 1
-                       9500 0 0 4 &mpic 2 1
+                       0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
+                       0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
+                       0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
+                       0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
 
                        /* IDSEL 0x12 func 6 - PCI slot 2 */
-                       9600 0 0 1 &mpic 3 1
-                       9600 0 0 2 &mpic 4 1
-                       9600 0 0 3 &mpic 1 1
-                       9600 0 0 4 &mpic 2 1
+                       0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
+                       0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
+                       0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
+                       0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
 
                        /* IDSEL 0x12 func 7 - PCI slot 2 */
-                       9700 0 0 1 &mpic 3 1
-                       9700 0 0 2 &mpic 4 1
-                       9700 0 0 3 &mpic 1 1
-                       9700 0 0 4 &mpic 2 1
+                       0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
+                       0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
+                       0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
+                       0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
 
                        // IDSEL 0x1c  USB
-                       e000 0 0 1 &i8259 c 2
-                       e100 0 0 2 &i8259 9 2
-                       e200 0 0 3 &i8259 a 2
-                       e300 0 0 4 &i8259 b 2
+                       0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
+                       0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
+                       0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
+                       0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 
                        // IDSEL 0x1d  Audio
-                       e800 0 0 1 &i8259 6 2
+                       0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 
                        // IDSEL 0x1e Legacy
-                       f000 0 0 1 &i8259 7 2
-                       f100 0 0 1 &i8259 7 2
+                       0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+                       0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 
                        // IDSEL 0x1f IDE/SATA
-                       f800 0 0 1 &i8259 e 2
-                       f900 0 0 1 &i8259 5 2
+                       0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+                       0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 
                        >;
 
                pcie@0 {
-                       reg = <0 0 0 0 0>;
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                       ranges = <02000000 0 80000000
-                                 02000000 0 80000000
-                                 0 20000000
+                       ranges = <0x2000000 0x0 0x80000000
+                                 0x2000000 0x0 0x80000000
+                                 0x0 0x20000000
 
-                                 01000000 0 00000000
-                                 01000000 0 00000000
-                                 0 00100000>;
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x100000>;
                        uli1575@0 {
-                               reg = <0 0 0 0 0>;
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
                                #size-cells = <2>;
                                #address-cells = <3>;
-                               ranges = <02000000 0 80000000
-                                         02000000 0 80000000
-                                         0 20000000
+                               ranges = <0x2000000 0x0 0x80000000
+                                         0x2000000 0x0 0x80000000
+                                         0x0 0x20000000
 
-                                         01000000 0 00000000
-                                         01000000 0 00000000
-                                         0 00100000>;
+                                         0x1000000 0x0 0x0
+                                         0x1000000 0x0 0x0
+                                         0x0 0x100000>;
                                isa@1e {
                                        device_type = "isa";
                                        #interrupt-cells = <2>;
                                        #size-cells = <1>;
                                        #address-cells = <2>;
-                                       reg = <f000 0 0 0 0>;
-                                       ranges = <1 0 01000000 0 0
-                                                 00001000>;
+                                       reg = <0xf000 0x0 0x0 0x0 0x0>;
+                                       ranges = <0x1 0x0 0x1000000 0x0 0x0
+                                                 0x1000>;
                                        interrupt-parent = <&i8259>;
 
                                        i8259: interrupt-controller@20 {
-                                               reg = <1 20 2
-                                                      1 a0 2
-                                                      1 4d0 2>;
+                                               reg = <0x1 0x20 0x2
+                                                      0x1 0xa0 0x2
+                                                      0x1 0x4d0 0x2>;
                                                interrupt-controller;
                                                device_type = "interrupt-controller";
                                                #address-cells = <0>;
                                        i8042@60 {
                                                #size-cells = <0>;
                                                #address-cells = <1>;
-                                               reg = <1 60 1 1 64 1>;
-                                               interrupts = <1 3 c 3>;
+                                               reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+                                               interrupts = <1 3 12 3>;
                                                interrupt-parent =
                                                        <&i8259>;
 
                                                keyboard@0 {
-                                                       reg = <0>;
+                                                       reg = <0x0>;
                                                        compatible = "pnpPNP,303";
                                                };
 
                                                mouse@1 {
-                                                       reg = <1>;
+                                                       reg = <0x1>;
                                                        compatible = "pnpPNP,f03";
                                                };
                                        };
 
                                        rtc@70 {
                                                compatible = "pnpPNP,b00";
-                                               reg = <1 70 2>;
+                                               reg = <0x1 0x70 0x2>;
                                        };
 
                                        gpio@400 {
-                                               reg = <1 400 80>;
+                                               reg = <0x1 0x400 0x80>;
                                        };
                                };
                        };
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <ffe09000 1000>;
-               bus-range = <0 ff>;
-               ranges = <02000000 0 a0000000 a0000000 0 20000000
-                         01000000 0 00000000 ffc10000 0 00010000>;
-               clock-frequency = <1fca055>;
+               reg = <0xffe09000 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+                         0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
+               clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
-               interrupts = <1a 2>;
-               interrupt-map-mask = <f800 0 0 7>;
+               interrupts = <26 2>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x0 */
-                       0000 0 0 1 &mpic 4 1
-                       0000 0 0 2 &mpic 5 1
-                       0000 0 0 3 &mpic 6 1
-                       0000 0 0 4 &mpic 7 1
+                       0000 0x0 0x0 0x1 &mpic 0x4 0x1
+                       0000 0x0 0x0 0x2 &mpic 0x5 0x1
+                       0000 0x0 0x0 0x3 &mpic 0x6 0x1
+                       0000 0x0 0x0 0x4 &mpic 0x7 0x1
                        >;
                pcie@0 {
-                       reg = <0 0 0 0 0>;
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                       ranges = <02000000 0 a0000000
-                                 02000000 0 a0000000
-                                 0 20000000
+                       ranges = <0x2000000 0x0 0xa0000000
+                                 0x2000000 0x0 0xa0000000
+                                 0x0 0x20000000
 
-                                 01000000 0 00000000
-                                 01000000 0 00000000
-                                 0 00100000>;
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x100000>;
                };
        };
 
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
-               reg = <ffe0a000 1000>;
-               bus-range = <0 ff>;
-               ranges = <02000000 0 c0000000 c0000000 0 20000000
-                         01000000 0 00000000 ffc20000 0 00010000>;
-               clock-frequency = <1fca055>;
+               reg = <0xffe0a000 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
+                         0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
+               clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
-               interrupts = <1b 2>;
-               interrupt-map-mask = <f800 0 0 7>;
+               interrupts = <27 2>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x0 */
-                       0000 0 0 1 &mpic 0 1
-                       0000 0 0 2 &mpic 1 1
-                       0000 0 0 3 &mpic 2 1
-                       0000 0 0 4 &mpic 3 1
+                       0000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0000 0x0 0x0 0x4 &mpic 0x3 0x1
                        >;
                pcie@0 {
-                       reg = <0 0 0 0 0>;
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                       ranges = <02000000 0 c0000000
-                                 02000000 0 c0000000
-                                 0 20000000
+                       ranges = <0x2000000 0x0 0xc0000000
+                                 0x2000000 0x0 0xc0000000
+                                 0x0 0x20000000
 
-                                 01000000 0 00000000
-                                 01000000 0 00000000
-                                 0 00100000>;
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x100000>;
                };
        };
 };