/* selected INTC register offsets */
-#define INTC_REVISION 0x0000
-#define INTC_SYSCONFIG 0x0010
-#define INTC_SYSSTATUS 0x0014
-#define INTC_CONTROL 0x0048
-#define INTC_MIR_CLEAR0 0x0088
-#define INTC_MIR_SET0 0x008c
+#define INTC_REVISION 0x0000
+#define INTC_SYSCONFIG 0x0010
+#define INTC_SYSSTATUS 0x0014
+#define INTC_CONTROL 0x0048
+#define INTC_MIR_CLEAR0 0x0088
+#define INTC_MIR_SET0 0x008c
+#define INTC_PENDING_IRQ0 0x0098
/*
* OMAP2 has a number of different interrupt controllers, each interrupt
intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
}
+int omap_irq_pending(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
+ struct omap_irq_bank *bank = irq_banks + i;
+ int irq;
+
+ for (irq = 0; irq < bank->nr_irqs; irq += 32)
+ if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
+ ((irq >> 5) << 5)))
+ return 1;
+ }
+ return 0;
+}
+
void __init omap_init_irq(void)
{
unsigned long nr_irqs = 0;
return 0;
}
-static int omap2_irq_pending(void)
-{
- u32 pending_reg = 0x480fe098;
- int i;
-
- for (i = 0; i < 4; i++) {
- if (omap_readl(pending_reg))
- return 1;
- pending_reg += 0x20;
- }
- return 0;
-}
-
static void omap2_enter_full_retention(void)
{
u32 l, sleep_time = 0;
/* One last check for pending IRQs to avoid extra latency due
* to sleeping unnecessarily. */
- if (omap2_irq_pending())
+ if (omap_irq_pending())
goto no_sleep;
serial_console_sleep(1);
*/
if (atomic_read(&sleep_block) == 0) {
timer_dyn_reprogram();
- if (omap2_irq_pending())
+ if (omap_irq_pending())
goto out;
}
omap2_enter_mpu_retention();
*/
timer_dyn_reprogram();
- if (omap2_irq_pending())
+ if (omap_irq_pending())
goto out;
omap2_enter_full_retention();