Commit
8b1f0bd44fe490ec631230c8c040753a2bda8caa introduced a bug that
caused non-CORE DPLL rates to be incorrectly set on boot in
omap3_noncore_dpll_enable(). Debugged by Tomi Valkeinen
<tomi.valkeinen@nokia.com> - thanks Tomi.
Also fix omap3_noncore_dpll_set_rate() to assign clk->rate after a
DPLL reprogram.
Tested on 3430SDP.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tomi Valkeinen <tomi.valkeinen@nokia.com>
Cc: Rick Bronson <rick@efn.org>
Cc: Timo Kokkonen <timo.t.kokkonen@nokia.com>
Cc: Sakari Poussa <sakari.poussa@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
static int omap3_noncore_dpll_enable(struct clk *clk)
{
int r;
- long rate;
struct dpll_data *dd;
if (clk == &dpll3_ck)
r = _omap3_noncore_dpll_lock(clk);
if (!r)
- clk->rate = rate;
+ clk->rate = omap2_get_dpll_rate(clk);
return r;
}
ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
dd->last_rounded_n, freqsel);
+ if (!ret)
+ clk->rate = rate;
+
}
omap3_dpll_recalc(clk);