c->chNo, tag,
musb_readl(base - DAVINCI_BASE_OFFSET,
DAVINCI_RXCPPI_BUFCNT0_REG + 4 *c->chNo),
- musb_readw(c->hw_ep->regs, MGC_O_HDRC_RXCSR),
+ musb_readw(c->hw_ep->regs, MUSB_RXCSR),
musb_readl(c->stateRam, 0 * 4), /* buf offset */
musb_readl(c->stateRam, 1 * 4), /* head ptr */
"F%08x L%08x .. %08x"
"\n",
c->chNo, tag,
- musb_readw(c->hw_ep->regs, MGC_O_HDRC_TXCSR),
+ musb_readw(c->hw_ep->regs, MUSB_TXCSR),
musb_readl(c->stateRam, 0 * 4), /* head ptr */
musb_readl(c->stateRam, 1 * 4), /* sop bd */
if (n_bds && rx->actualLen) {
void *__iomem regs = rx->hw_ep->regs;
- val = musb_readw(regs, MGC_O_HDRC_RXCSR);
+ val = musb_readw(regs, MUSB_RXCSR);
if (!(val & MGC_M_RXCSR_H_REQPKT)) {
val |= MGC_M_RXCSR_H_REQPKT | MGC_M_RXCSR_H_WZC_BITS;
- musb_writew(regs, MGC_O_HDRC_RXCSR, val);
+ musb_writew(regs, MUSB_RXCSR, val);
/* flush writebufer */
- val = musb_readw(regs, MGC_O_HDRC_RXCSR);
+ val = musb_readw(regs, MUSB_RXCSR);
}
}
return n_bds;
WARN_ON(rx->activeQueueHead);
}
musb_ep_select(cppi->pCoreBase, rx->chNo + 1);
- csr = musb_readw(regs, MGC_O_HDRC_RXCSR);
+ csr = musb_readw(regs, MUSB_RXCSR);
if (csr & MGC_M_RXCSR_DMAENAB) {
DBG(4, "list%d %p/%p, last %08x%s, csr %04x\n",
rx->chNo,
/* REVISIT seems like "autoreq all but EOP" doesn't...
* setting it here "should" be racey, but seems to work
*/
- csr = musb_readw(rx->hw_ep->regs, MGC_O_HDRC_RXCSR);
+ csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR);
if (is_host_active(cppi->musb)
&& bd
&& !(csr & MGC_M_RXCSR_H_REQPKT)) {
csr |= MGC_M_RXCSR_H_REQPKT;
- musb_writew(regs, MGC_O_HDRC_RXCSR,
+ musb_writew(regs, MUSB_RXCSR,
MGC_M_RXCSR_H_WZC_BITS | csr);
- csr = musb_readw(rx->hw_ep->regs, MGC_O_HDRC_RXCSR);
+ csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR);
}
} else {
rx->activeQueueHead = NULL;
int csr;
csr = musb_readw(hw_ep->regs,
- MGC_O_HDRC_TXCSR);
+ MUSB_TXCSR);
if (csr & MGC_M_TXCSR_TXPKTRDY)
#endif
bReqComplete = 0;
* an appropriate status code.
*/
- regVal = musb_readw(regs, MGC_O_HDRC_TXCSR);
+ regVal = musb_readw(regs, MUSB_TXCSR);
regVal &= ~MGC_M_TXCSR_DMAENAB;
regVal |= MGC_M_TXCSR_FLUSHFIFO;
- musb_writew(regs, MGC_O_HDRC_TXCSR, regVal);
- musb_writew(regs, MGC_O_HDRC_TXCSR, regVal);
+ musb_writew(regs, MUSB_TXCSR, regVal);
+ musb_writew(regs, MUSB_TXCSR, regVal);
/* re-enable interrupt */
if (enabled)
musb_writel(regBase, DAVINCI_AUTOREQ_REG, regVal);
}
- csr = musb_readw(regs, MGC_O_HDRC_RXCSR);
+ csr = musb_readw(regs, MUSB_RXCSR);
/* for host, clear (just) ReqPkt at end of current packet(s) */
if (is_host_active(otgCh->pController->musb)) {
/* clear dma enable */
csr &= ~(MGC_M_RXCSR_DMAENAB);
- musb_writew(regs, MGC_O_HDRC_RXCSR, csr);
- csr = musb_readw(regs, MGC_O_HDRC_RXCSR);
+ musb_writew(regs, MUSB_RXCSR, csr);
+ csr = musb_readw(regs, MUSB_RXCSR);
/* quiesce: wait for current dma to finish (if not cleanup)
* we can't use bit zero of stateram->sopDescPtr since that
DAVINCI_USB_USBINT_MASK
| DAVINCI_USB_TXINT_MASK
| DAVINCI_USB_RXINT_MASK);
- musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, 0);
+ musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
if (is_dma_capable() && !dma_off)
/* We poll because DaVinci's won't expose several OTG-critical
* status change events (from the transceiver) otherwise.
*/
- devctl = musb_readb(mregs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(mregs, MUSB_DEVCTL);
DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
spin_lock_irqsave(&musb->lock, flags);
* NOTE setting the session flag is _supposed_ to trigger
* SRP, but clearly it doesn't.
*/
- musb_writeb(mregs, MGC_O_HDRC_DEVCTL,
+ musb_writeb(mregs, MUSB_DEVCTL,
devctl | MGC_M_DEVCTL_SESSION);
- devctl = musb_readb(mregs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(mregs, MUSB_DEVCTL);
if (devctl & MGC_M_DEVCTL_BDEVICE)
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
else
if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
void *__iomem mregs = musb->mregs;
- u8 devctl = musb_readb(mregs, MGC_O_HDRC_DEVCTL);
+ u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
int err = musb->int_usb & MGC_M_INTR_VBUSERROR;
err = is_host_enabled(musb)
* long time to fall, especially on EVM with huge C133.
*/
do {
- devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
if (!(devctl & MGC_M_DEVCTL_VBUS))
break;
if ((devctl & MGC_M_DEVCTL_VBUS) != warn) {
musb_ep_select(mbase, epnum);
if (is_in)
- tmp = musb_readw(regs, MGC_O_HDRC_TXCSR)
+ tmp = musb_readw(regs, MUSB_TXCSR)
& MGC_M_TXCSR_P_SENDSTALL;
else
- tmp = musb_readw(regs, MGC_O_HDRC_RXCSR)
+ tmp = musb_readw(regs, MUSB_RXCSR)
& MGC_M_RXCSR_P_SENDSTALL;
musb_ep_select(mbase, 0);
u8 devctl;
DBG(1, "HNP: Setting HR\n");
- devctl = musb_readb(mbase, MGC_O_HDRC_DEVCTL);
- musb_writeb(mbase, MGC_O_HDRC_DEVCTL, devctl | MGC_M_DEVCTL_HR);
+ devctl = musb_readb(mbase, MUSB_DEVCTL);
+ musb_writeb(mbase, MUSB_DEVCTL, devctl | MGC_M_DEVCTL_HR);
}
/*
musb_ep_select(mbase, epnum);
if (is_in) {
csr = musb_readw(regs,
- MGC_O_HDRC_TXCSR);
+ MUSB_TXCSR);
if (csr & MGC_M_TXCSR_FIFONOTEMPTY)
csr |= MGC_M_TXCSR_FLUSHFIFO;
csr |= MGC_M_TXCSR_P_SENDSTALL
| MGC_M_TXCSR_CLRDATATOG
| MGC_M_TXCSR_P_WZC_BITS;
- musb_writew(regs, MGC_O_HDRC_TXCSR,
+ musb_writew(regs, MUSB_TXCSR,
csr);
} else {
csr = musb_readw(regs,
- MGC_O_HDRC_RXCSR);
+ MUSB_RXCSR);
csr |= MGC_M_RXCSR_P_SENDSTALL
| MGC_M_RXCSR_FLUSHFIFO
| MGC_M_RXCSR_CLRDATATOG
| MGC_M_TXCSR_P_WZC_BITS;
- musb_writew(regs, MGC_O_HDRC_RXCSR,
+ musb_writew(regs, MUSB_RXCSR,
csr);
}
unsigned len = req->length - req->actual;
/* read the buffer */
- tmp = musb_readb(regs, MGC_O_HDRC_COUNT0);
+ tmp = musb_readb(regs, MUSB_COUNT0);
if (tmp > len) {
req->status = -EOVERFLOW;
tmp = len;
req = NULL;
} else
tmp = MGC_M_CSR0_P_SVDRXPKTRDY | MGC_M_CSR0_P_SENDSTALL;
- musb_writew(regs, MGC_O_HDRC_CSR0, tmp);
+ musb_writew(regs, MUSB_CSR0, tmp);
/* NOTE: we "should" hold off reporting DATAEND and going to
if (!request) {
// WARN_ON(1);
- DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MGC_O_HDRC_CSR0));
+ DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
return;
}
request = NULL;
/* send it out, triggering a "txpktrdy cleared" irq */
- musb_writew(regs, MGC_O_HDRC_CSR0, csr);
+ musb_writew(regs, MUSB_CSR0, csr);
/* report completions as soon as the fifo's loaded; there's no
* win in waiting till this last packet gets acked. (other than
musb->ep0_state = MGC_END0_STAGE_ACKWAIT;
} else if (req->bRequestType & USB_DIR_IN) {
musb->ep0_state = MGC_END0_STAGE_TX;
- musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SVDRXPKTRDY);
- while ((musb_readw(regs, MGC_O_HDRC_CSR0)
+ musb_writew(regs, MUSB_CSR0, MGC_M_CSR0_P_SVDRXPKTRDY);
+ while ((musb_readw(regs, MUSB_CSR0)
& MGC_M_CSR0_RXPKTRDY) != 0)
cpu_relax();
musb->ackpend = 0;
irqreturn_t retval = IRQ_NONE;
musb_ep_select(mbase, 0); /* select ep0 */
- csr = musb_readw(regs, MGC_O_HDRC_CSR0);
- len = musb_readb(regs, MGC_O_HDRC_COUNT0);
+ csr = musb_readw(regs, MUSB_CSR0);
+ len = musb_readb(regs, MUSB_COUNT0);
DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
csr, len,
- musb_readb(mbase, MGC_O_HDRC_FADDR),
+ musb_readb(mbase, MUSB_FADDR),
decode_ep0stage(musb->ep0_state));
/* I sent a stall.. need to acknowledge it now.. */
if (csr & MGC_M_CSR0_P_SENTSTALL) {
- musb_writew(regs, MGC_O_HDRC_CSR0,
+ musb_writew(regs, MUSB_CSR0,
csr & ~MGC_M_CSR0_P_SENTSTALL);
retval = IRQ_HANDLED;
musb->ep0_state = MGC_END0_STAGE_SETUP;
- csr = musb_readw(regs, MGC_O_HDRC_CSR0);
+ csr = musb_readw(regs, MUSB_CSR0);
}
/* request ended "early" */
if (csr & MGC_M_CSR0_P_SETUPEND) {
- musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SVDSETUPEND);
+ musb_writew(regs, MUSB_CSR0, MGC_M_CSR0_P_SVDSETUPEND);
retval = IRQ_HANDLED;
musb->ep0_state = MGC_END0_STAGE_SETUP;
- csr = musb_readw(regs, MGC_O_HDRC_CSR0);
+ csr = musb_readw(regs, MUSB_CSR0);
/* NOTE: request may need completion */
}
*/
if (musb->set_address) {
musb->set_address = FALSE;
- musb_writeb(mbase, MGC_O_HDRC_FADDR, musb->address);
+ musb_writeb(mbase, MUSB_FADDR, musb->address);
}
/* enter test mode if needed (exit by reset) */
if (MGC_M_TEST_PACKET == musb->test_mode_nr)
musb_load_testpacket(musb);
- musb_writeb(mbase, MGC_O_HDRC_TESTMODE,
+ musb_writeb(mbase, MUSB_TESTMODE,
musb->test_mode_nr);
}
/* FALLTHROUGH */
printk(KERN_NOTICE "%s: peripheral reset "
"irq lost!\n",
musb_driver_name);
- power = musb_readb(mbase, MGC_O_HDRC_POWER);
+ power = musb_readb(mbase, MUSB_POWER);
musb->g.speed = (power & MGC_M_POWER_HSMODE)
? USB_SPEED_HIGH : USB_SPEED_FULL;
musb->ackpend |= MGC_M_CSR0_P_SENDSTALL;
musb->ep0_state = MGC_END0_STAGE_SETUP;
finish:
- musb_writew(regs, MGC_O_HDRC_CSR0,
+ musb_writew(regs, MUSB_CSR0,
musb->ackpend);
musb->ackpend = 0;
}
default:
/* "can't happen" */
WARN_ON(1);
- musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SENDSTALL);
+ musb_writew(regs, MUSB_CSR0, MGC_M_CSR0_P_SENDSTALL);
musb->ep0_state = MGC_END0_STAGE_SETUP;
break;
}
status = -EINVAL;
else {
musb->ep0_state = MGC_END0_STAGE_STATUSIN;
- musb_writew(regs, MGC_O_HDRC_CSR0,
+ musb_writew(regs, MUSB_CSR0,
musb->ackpend | MGC_M_CSR0_P_DATAEND);
musb->ackpend = 0;
musb_g_ep0_giveback(ep->musb, r);
* (after SETUP is acked) are racey.
*/
} else if (musb->ackpend) {
- musb_writew(regs, MGC_O_HDRC_CSR0, musb->ackpend);
+ musb_writew(regs, MUSB_CSR0, musb->ackpend);
musb->ackpend = 0;
}
status = 0;
musb_ep_select(base, 0);
- csr = musb_readw(regs, MGC_O_HDRC_CSR0);
+ csr = musb_readw(regs, MUSB_CSR0);
csr |= MGC_M_CSR0_P_SENDSTALL;
- musb_writew(regs, MGC_O_HDRC_CSR0, csr);
+ musb_writew(regs, MUSB_CSR0, csr);
musb->ep0_state = MGC_END0_STAGE_SETUP;
break;
default:
struct dma_controller *c = ep->musb->dma_controller;
int value;
if (ep->is_in) {
- musb_writew(epio, MGC_O_HDRC_TXCSR,
+ musb_writew(epio, MUSB_TXCSR,
0 | MGC_M_TXCSR_FLUSHFIFO);
- musb_writew(epio, MGC_O_HDRC_TXCSR,
+ musb_writew(epio, MUSB_TXCSR,
0 | MGC_M_TXCSR_FLUSHFIFO);
} else {
- musb_writew(epio, MGC_O_HDRC_RXCSR,
+ musb_writew(epio, MUSB_RXCSR,
0 | MGC_M_RXCSR_FLUSHFIFO);
- musb_writew(epio, MGC_O_HDRC_RXCSR,
+ musb_writew(epio, MUSB_RXCSR,
0 | MGC_M_RXCSR_FLUSHFIFO);
}
}
/* read TXCSR before */
- csr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ csr = musb_readw(epio, MUSB_TXCSR);
request = &req->request;
fifo_count = min(max_ep_writesize(musb, musb_ep),
| MGC_M_TXCSR_MODE);
csr &= ~MGC_M_TXCSR_P_UNDERRUN;
- musb_writew(epio, MGC_O_HDRC_TXCSR, csr);
+ musb_writew(epio, MUSB_TXCSR, csr);
}
}
| MGC_M_TXCSR_P_UNDERRUN
| MGC_M_TXCSR_TXPKTRDY);
csr |= MGC_M_TXCSR_MODE | MGC_M_TXCSR_DMAENAB;
- musb_writew(epio, MGC_O_HDRC_TXCSR,
+ musb_writew(epio, MUSB_TXCSR,
(MGC_M_TXCSR_P_WZC_BITS & ~MGC_M_TXCSR_P_UNDERRUN)
| csr);
/* ensure writebuffer is empty */
- csr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ csr = musb_readw(epio, MUSB_TXCSR);
/* NOTE host side sets DMAENAB later than this; both are
* OK since the transfer dma glue (between CPPI and Mentor
request->actual += fifo_count;
csr |= MGC_M_TXCSR_TXPKTRDY;
csr &= ~MGC_M_TXCSR_P_UNDERRUN;
- musb_writew(epio, MGC_O_HDRC_TXCSR, csr);
+ musb_writew(epio, MUSB_TXCSR, csr);
}
/* host may already have the data when this message shows... */
DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
musb_ep->end_point.name, use_dma ? "dma" : "pio",
request->actual, request->length,
- musb_readw(epio, MGC_O_HDRC_TXCSR),
+ musb_readw(epio, MUSB_TXCSR),
fifo_count,
- musb_readw(epio, MGC_O_HDRC_TXMAXP));
+ musb_readw(epio, MUSB_TXMAXP));
}
/*
musb_ep_select(mbase, epnum);
request = next_request(musb_ep);
- csr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ csr = musb_readw(epio, MUSB_TXCSR);
DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
dma = is_dma_capable() ? musb_ep->dma : NULL;
if (csr & MGC_M_TXCSR_P_SENTSTALL) {
csr |= MGC_M_TXCSR_P_WZC_BITS;
csr &= ~MGC_M_TXCSR_P_SENTSTALL;
- musb_writew(epio, MGC_O_HDRC_TXCSR, csr);
+ musb_writew(epio, MUSB_TXCSR, csr);
if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
dma->status = MGC_DMA_STATUS_CORE_ABORT;
musb->dma_controller->channel_abort(dma);
csr |= MGC_M_TXCSR_P_WZC_BITS;
csr &= ~(MGC_M_TXCSR_P_UNDERRUN
| MGC_M_TXCSR_TXPKTRDY);
- musb_writew(epio, MGC_O_HDRC_TXCSR, csr);
+ musb_writew(epio, MUSB_TXCSR, csr);
DBG(20, "underrun on ep%d, req %p\n", epnum, request);
}
csr &= ~(MGC_M_TXCSR_DMAENAB
| MGC_M_TXCSR_P_UNDERRUN
| MGC_M_TXCSR_TXPKTRDY);
- musb_writew(epio, MGC_O_HDRC_TXCSR, csr);
+ musb_writew(epio, MUSB_TXCSR, csr);
/* ensure writebuffer is empty */
- csr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ csr = musb_readw(epio, MUSB_TXCSR);
request->actual += musb_ep->dma->actual_len;
DBG(4, "TXCSR%d %04x, dma off, "
"len %Zd, req %p\n",
break;
DBG(4, "sending zero pkt\n");
- musb_writew(epio, MGC_O_HDRC_TXCSR,
+ musb_writew(epio, MUSB_TXCSR,
MGC_M_TXCSR_MODE
| MGC_M_TXCSR_TXPKTRDY);
request->zero = 0;
* FIXME revisit for stalls too...
*/
musb_ep_select(mbase, epnum);
- csr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ csr = musb_readw(epio, MUSB_TXCSR);
if (csr & MGC_M_TXCSR_FIFONOTEMPTY)
break;
request = musb_ep->desc
u16 fifo_count = 0;
u16 len = musb_ep->packet_sz;
- csr = musb_readw(epio, MGC_O_HDRC_RXCSR);
+ csr = musb_readw(epio, MUSB_RXCSR);
if (is_cppi_enabled() && musb_ep->dma) {
struct dma_controller *c = musb->dma_controller;
csr &= ~(MGC_M_RXCSR_AUTOCLEAR
| MGC_M_RXCSR_DMAMODE);
csr |= MGC_M_RXCSR_DMAENAB | MGC_M_RXCSR_P_WZC_BITS;
- musb_writew(epio, MGC_O_HDRC_RXCSR, csr);
+ musb_writew(epio, MUSB_RXCSR, csr);
return;
}
}
if (csr & MGC_M_RXCSR_RXPKTRDY) {
- len = musb_readw(epio, MGC_O_HDRC_RXCOUNT);
+ len = musb_readw(epio, MUSB_RXCOUNT);
if (request->actual < request->length) {
#ifdef CONFIG_USB_INVENTRA_DMA
if (is_dma_capable() && musb_ep->dma) {
disabling MGC_M_RXCSR_DMAMODE) is required
to get DMAReq to activate
*/
- musb_writew(epio, MGC_O_HDRC_RXCSR,
+ musb_writew(epio, MUSB_RXCSR,
csr | MGC_M_RXCSR_DMAMODE);
#endif
- musb_writew(epio, MGC_O_HDRC_RXCSR,
+ musb_writew(epio, MUSB_RXCSR,
csr);
if (request->actual < request->length) {
/* ack the read! */
csr |= MGC_M_RXCSR_P_WZC_BITS;
csr &= ~MGC_M_RXCSR_RXPKTRDY;
- musb_writew(epio, MGC_O_HDRC_RXCSR, csr);
+ musb_writew(epio, MUSB_RXCSR, csr);
}
}
request = next_request(musb_ep);
- csr = musb_readw(epio, MGC_O_HDRC_RXCSR);
+ csr = musb_readw(epio, MUSB_RXCSR);
dma = is_dma_capable() ? musb_ep->dma : NULL;
DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
csr |= MGC_M_RXCSR_P_WZC_BITS;
csr &= ~MGC_M_RXCSR_P_SENTSTALL;
- musb_writew(epio, MGC_O_HDRC_RXCSR, csr);
+ musb_writew(epio, MUSB_RXCSR, csr);
if (request)
musb_g_giveback(musb_ep, request, -EPIPE);
if (csr & MGC_M_RXCSR_P_OVERRUN) {
// csr |= MGC_M_RXCSR_P_WZC_BITS;
csr &= ~MGC_M_RXCSR_P_OVERRUN;
- musb_writew(epio, MGC_O_HDRC_RXCSR, csr);
+ musb_writew(epio, MUSB_RXCSR, csr);
DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
if (request && request->status == -EINPROGRESS)
csr &= ~(MGC_M_RXCSR_AUTOCLEAR
| MGC_M_RXCSR_DMAENAB
| MGC_M_RXCSR_DMAMODE);
- musb_writew(epio, MGC_O_HDRC_RXCSR,
+ musb_writew(epio, MUSB_RXCSR,
MGC_M_RXCSR_P_WZC_BITS | csr);
request->actual += musb_ep->dma->actual_len;
DBG(4, "RXCSR%d %04x, dma off, %04x, len %Zd, req %p\n",
epnum, csr,
- musb_readw(epio, MGC_O_HDRC_RXCSR),
+ musb_readw(epio, MUSB_RXCSR),
musb_ep->dma->actual_len, request);
#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
& (musb_ep->packet_sz - 1))) {
/* ack the read! */
csr &= ~MGC_M_RXCSR_RXPKTRDY;
- musb_writew(epio, MGC_O_HDRC_RXCSR, csr);
+ musb_writew(epio, MUSB_RXCSR, csr);
}
/* incomplete, and not short? wait for next IN packet */
/* don't start more i/o till the stall clears */
musb_ep_select(mbase, epnum);
- csr = musb_readw(epio, MGC_O_HDRC_RXCSR);
+ csr = musb_readw(epio, MUSB_RXCSR);
if (csr & MGC_M_RXCSR_P_SENDSTALL)
goto done;
}
*/
musb_ep_select(mbase, epnum);
if (desc->bEndpointAddress & USB_DIR_IN) {
- u16 wIntrTxE = musb_readw(mbase, MGC_O_HDRC_INTRTXE);
+ u16 wIntrTxE = musb_readw(mbase, MUSB_INTRTXE);
if (hw_ep->is_shared_fifo)
musb_ep->is_in = 1;
goto fail;
wIntrTxE |= (1 << epnum);
- musb_writew(mbase, MGC_O_HDRC_INTRTXE, wIntrTxE);
+ musb_writew(mbase, MUSB_INTRTXE, wIntrTxE);
/* REVISIT if can_bulk_split(), use by updating "tmp";
* likewise high bandwidth periodic tx
*/
- musb_writew(regs, MGC_O_HDRC_TXMAXP, tmp);
+ musb_writew(regs, MUSB_TXMAXP, tmp);
csr = MGC_M_TXCSR_MODE | MGC_M_TXCSR_CLRDATATOG;
- if (musb_readw(regs, MGC_O_HDRC_TXCSR)
+ if (musb_readw(regs, MUSB_TXCSR)
& MGC_M_TXCSR_FIFONOTEMPTY)
csr |= MGC_M_TXCSR_FLUSHFIFO;
if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
csr |= MGC_M_TXCSR_P_ISO;
/* set twice in case of double buffering */
- musb_writew(regs, MGC_O_HDRC_TXCSR, csr);
+ musb_writew(regs, MUSB_TXCSR, csr);
/* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
- musb_writew(regs, MGC_O_HDRC_TXCSR, csr);
+ musb_writew(regs, MUSB_TXCSR, csr);
} else {
- u16 wIntrRxE = musb_readw(mbase, MGC_O_HDRC_INTRRXE);
+ u16 wIntrRxE = musb_readw(mbase, MUSB_INTRRXE);
if (hw_ep->is_shared_fifo)
musb_ep->is_in = 0;
goto fail;
wIntrRxE |= (1 << epnum);
- musb_writew(mbase, MGC_O_HDRC_INTRRXE, wIntrRxE);
+ musb_writew(mbase, MUSB_INTRRXE, wIntrRxE);
/* REVISIT if can_bulk_combine() use by updating "tmp"
* likewise high bandwidth periodic rx
*/
- musb_writew(regs, MGC_O_HDRC_RXMAXP, tmp);
+ musb_writew(regs, MUSB_RXMAXP, tmp);
/* force shared fifo to OUT-only mode */
if (hw_ep->is_shared_fifo) {
- csr = musb_readw(regs, MGC_O_HDRC_TXCSR);
+ csr = musb_readw(regs, MUSB_TXCSR);
csr &= ~(MGC_M_TXCSR_MODE | MGC_M_TXCSR_TXPKTRDY);
- musb_writew(regs, MGC_O_HDRC_TXCSR, csr);
+ musb_writew(regs, MUSB_TXCSR, csr);
}
csr = MGC_M_RXCSR_FLUSHFIFO | MGC_M_RXCSR_CLRDATATOG;
csr |= MGC_M_RXCSR_DISNYET;
/* set twice in case of double buffering */
- musb_writew(regs, MGC_O_HDRC_RXCSR, csr);
- musb_writew(regs, MGC_O_HDRC_RXCSR, csr);
+ musb_writew(regs, MUSB_RXCSR, csr);
+ musb_writew(regs, MUSB_RXCSR, csr);
}
/* NOTE: all the I/O code _should_ work fine without DMA, in case
/* zero the endpoint sizes */
if (musb_ep->is_in) {
- u16 wIntrTxE = musb_readw(musb->mregs, MGC_O_HDRC_INTRTXE);
+ u16 wIntrTxE = musb_readw(musb->mregs, MUSB_INTRTXE);
wIntrTxE &= ~(1 << epnum);
- musb_writew(musb->mregs, MGC_O_HDRC_INTRTXE, wIntrTxE);
- musb_writew(epio, MGC_O_HDRC_TXMAXP, 0);
+ musb_writew(musb->mregs, MUSB_INTRTXE, wIntrTxE);
+ musb_writew(epio, MUSB_TXMAXP, 0);
} else {
- u16 wIntrRxE = musb_readw(musb->mregs, MGC_O_HDRC_INTRRXE);
+ u16 wIntrRxE = musb_readw(musb->mregs, MUSB_INTRRXE);
wIntrRxE &= ~(1 << epnum);
- musb_writew(musb->mregs, MGC_O_HDRC_INTRRXE, wIntrRxE);
- musb_writew(epio, MGC_O_HDRC_RXMAXP, 0);
+ musb_writew(musb->mregs, MUSB_INTRRXE, wIntrRxE);
+ musb_writew(epio, MUSB_RXMAXP, 0);
}
musb_ep->desc = NULL;
/* cannot portably stall with non-empty FIFO */
request = to_musb_request(next_request(musb_ep));
if (value && musb_ep->is_in) {
- wCsr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ wCsr = musb_readw(epio, MUSB_TXCSR);
if (wCsr & MGC_M_TXCSR_FIFONOTEMPTY) {
DBG(3, "%s fifo busy, cannot halt\n", ep->name);
spin_unlock_irqrestore(&musb->lock, flags);
/* set/clear the stall and toggle bits */
DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
if (musb_ep->is_in) {
- wCsr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ wCsr = musb_readw(epio, MUSB_TXCSR);
if (wCsr & MGC_M_TXCSR_FIFONOTEMPTY)
wCsr |= MGC_M_TXCSR_FLUSHFIFO;
wCsr |= MGC_M_TXCSR_P_WZC_BITS
wCsr &= ~(MGC_M_TXCSR_P_SENDSTALL
| MGC_M_TXCSR_P_SENTSTALL);
wCsr &= ~MGC_M_TXCSR_TXPKTRDY;
- musb_writew(epio, MGC_O_HDRC_TXCSR, wCsr);
+ musb_writew(epio, MUSB_TXCSR, wCsr);
} else {
- wCsr = musb_readw(epio, MGC_O_HDRC_RXCSR);
+ wCsr = musb_readw(epio, MUSB_RXCSR);
wCsr |= MGC_M_RXCSR_P_WZC_BITS
| MGC_M_RXCSR_FLUSHFIFO
| MGC_M_RXCSR_CLRDATATOG;
else
wCsr &= ~(MGC_M_RXCSR_P_SENDSTALL
| MGC_M_RXCSR_P_SENTSTALL);
- musb_writew(epio, MGC_O_HDRC_RXCSR, wCsr);
+ musb_writew(epio, MUSB_RXCSR, wCsr);
}
done:
musb_ep_select(mbase, epnum);
/* FIXME return zero unless RXPKTRDY is set */
- retval = musb_readw(epio, MGC_O_HDRC_RXCOUNT);
+ retval = musb_readw(epio, MUSB_RXCOUNT);
spin_unlock_irqrestore(&musb->lock, flags);
}
musb_ep_select(mbase, (u8) nEnd);
/* disable interrupts */
- wIntrTxE = musb_readw(mbase, MGC_O_HDRC_INTRTXE);
- musb_writew(mbase, MGC_O_HDRC_INTRTXE, wIntrTxE & ~(1 << nEnd));
+ wIntrTxE = musb_readw(mbase, MUSB_INTRTXE);
+ musb_writew(mbase, MUSB_INTRTXE, wIntrTxE & ~(1 << nEnd));
if (musb_ep->is_in) {
- wCsr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ wCsr = musb_readw(epio, MUSB_TXCSR);
if (wCsr & MGC_M_TXCSR_FIFONOTEMPTY) {
wCsr |= MGC_M_TXCSR_FLUSHFIFO | MGC_M_TXCSR_P_WZC_BITS;
- musb_writew(epio, MGC_O_HDRC_TXCSR, wCsr);
+ musb_writew(epio, MUSB_TXCSR, wCsr);
/* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
- musb_writew(epio, MGC_O_HDRC_TXCSR, wCsr);
+ musb_writew(epio, MUSB_TXCSR, wCsr);
}
} else {
- wCsr = musb_readw(epio, MGC_O_HDRC_RXCSR);
+ wCsr = musb_readw(epio, MUSB_RXCSR);
wCsr |= MGC_M_RXCSR_FLUSHFIFO | MGC_M_RXCSR_P_WZC_BITS;
- musb_writew(epio, MGC_O_HDRC_RXCSR, wCsr);
- musb_writew(epio, MGC_O_HDRC_RXCSR, wCsr);
+ musb_writew(epio, MUSB_RXCSR, wCsr);
+ musb_writew(epio, MUSB_RXCSR, wCsr);
}
/* re-enable interrupt */
- musb_writew(mbase, MGC_O_HDRC_INTRTXE, wIntrTxE);
+ musb_writew(mbase, MUSB_INTRTXE, wIntrTxE);
spin_unlock_irqrestore(&musb->lock, flags);
}
{
struct musb *musb = gadget_to_musb(gadget);
- return (int)musb_readw(musb->mregs, MGC_O_HDRC_FRAME);
+ return (int)musb_readw(musb->mregs, MUSB_FRAME);
}
static int musb_gadget_wakeup(struct usb_gadget *gadget)
goto done;
case OTG_STATE_B_IDLE:
/* Start SRP ... OTG not required. */
- devctl = musb_readb(mregs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(mregs, MUSB_DEVCTL);
DBG(2, "Sending SRP: devctl: %02x\n", devctl);
devctl |= MGC_M_DEVCTL_SESSION;
- musb_writeb(mregs, MGC_O_HDRC_DEVCTL, devctl);
- devctl = musb_readb(mregs, MGC_O_HDRC_DEVCTL);
+ musb_writeb(mregs, MUSB_DEVCTL, devctl);
+ devctl = musb_readb(mregs, MUSB_DEVCTL);
retries = 100;
while (!(devctl & MGC_M_DEVCTL_SESSION)) {
- devctl = musb_readb(mregs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(mregs, MUSB_DEVCTL);
if (retries-- < 1)
break;
}
retries = 10000;
while (devctl & MGC_M_DEVCTL_SESSION) {
- devctl = musb_readb(mregs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(mregs, MUSB_DEVCTL);
if (retries-- < 1)
break;
}
status = 0;
- power = musb_readb(mregs, MGC_O_HDRC_POWER);
+ power = musb_readb(mregs, MUSB_POWER);
power |= MGC_M_POWER_RESUME;
- musb_writeb(mregs, MGC_O_HDRC_POWER, power);
+ musb_writeb(mregs, MUSB_POWER, power);
DBG(2, "issue wakeup\n");
/* FIXME do this next chunk in a timer callback, no udelay */
mdelay(2);
- power = musb_readb(mregs, MGC_O_HDRC_POWER);
+ power = musb_readb(mregs, MUSB_POWER);
power &= ~MGC_M_POWER_RESUME;
- musb_writeb(mregs, MGC_O_HDRC_POWER, power);
+ musb_writeb(mregs, MUSB_POWER, power);
done:
spin_unlock_irqrestore(&musb->lock, flags);
return status;
{
u8 power;
- power = musb_readb(musb->mregs, MGC_O_HDRC_POWER);
+ power = musb_readb(musb->mregs, MUSB_POWER);
if (is_on)
power |= MGC_M_POWER_SOFTCONN;
else
DBG(3, "gadget %s D+ pullup %s\n",
musb->gadget_driver->function, is_on ? "on" : "off");
- musb_writeb(musb->mregs, MGC_O_HDRC_POWER, power);
+ musb_writeb(musb->mregs, MUSB_POWER, power);
}
#if 0
{
u8 devctl;
- devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
DBG(3, "devctl %02x\n", devctl);
switch (musb->xceiv.state) {
void musb_g_disconnect(struct musb *musb)
{
void __iomem *mregs = musb->mregs;
- u8 devctl = musb_readb(mregs, MGC_O_HDRC_DEVCTL);
+ u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
DBG(3, "devctl %02x\n", devctl);
/* clear HR */
- musb_writeb(mregs, MGC_O_HDRC_DEVCTL, devctl & MGC_M_DEVCTL_SESSION);
+ musb_writeb(mregs, MUSB_DEVCTL, devctl & MGC_M_DEVCTL_SESSION);
/* don't draw vbus until new b-default session */
(void) musb_gadget_vbus_draw(&musb->g, 0);
__acquires(musb->lock)
{
void __iomem *mbase = musb->mregs;
- u8 devctl = musb_readb(mbase, MGC_O_HDRC_DEVCTL);
+ u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
u8 power;
DBG(3, "<== %s addr=%x driver '%s'\n",
(devctl & MGC_M_DEVCTL_BDEVICE)
? "B-Device" : "A-Device",
- musb_readb(mbase, MGC_O_HDRC_FADDR),
+ musb_readb(mbase, MUSB_FADDR),
musb->gadget_driver
? musb->gadget_driver->driver.name
: NULL
/* clear HR */
else if (devctl & MGC_M_DEVCTL_HR)
- musb_writeb(mbase, MGC_O_HDRC_DEVCTL, MGC_M_DEVCTL_SESSION);
+ musb_writeb(mbase, MUSB_DEVCTL, MGC_M_DEVCTL_SESSION);
/* what speed did we negotiate? */
- power = musb_readb(mbase, MGC_O_HDRC_POWER);
+ power = musb_readb(mbase, MUSB_POWER);
musb->g.speed = (power & MGC_M_POWER_HSMODE)
? USB_SPEED_HIGH : USB_SPEED_FULL;
u16 csr;
int retries = 1000;
- csr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ csr = musb_readw(epio, MUSB_TXCSR);
while (csr & MGC_M_TXCSR_FIFONOTEMPTY) {
DBG(5, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
csr |= MGC_M_TXCSR_FLUSHFIFO;
- musb_writew(epio, MGC_O_HDRC_TXCSR, csr);
- csr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ musb_writew(epio, MUSB_TXCSR, csr);
+ csr = musb_readw(epio, MUSB_TXCSR);
if (retries-- < 1) {
ERR("Could not flush host TX fifo: csr: %04x\n", csr);
return;
/* NOTE: no locks here; caller should lock and select EP */
if (ep->epnum) {
- txcsr = musb_readw(ep->regs, MGC_O_HDRC_TXCSR);
+ txcsr = musb_readw(ep->regs, MUSB_TXCSR);
txcsr |= MGC_M_TXCSR_TXPKTRDY | MGC_M_TXCSR_H_WZC_BITS;
- musb_writew(ep->regs, MGC_O_HDRC_TXCSR, txcsr);
+ musb_writew(ep->regs, MUSB_TXCSR, txcsr);
} else {
txcsr = MGC_M_CSR0_H_SETUPPKT | MGC_M_CSR0_TXPKTRDY;
- musb_writew(ep->regs, MGC_O_HDRC_CSR0, txcsr);
+ musb_writew(ep->regs, MUSB_CSR0, txcsr);
}
}
u16 txcsr;
/* NOTE: no locks here; caller should lock and select EP */
- txcsr = musb_readw(ep->regs, MGC_O_HDRC_TXCSR);
+ txcsr = musb_readw(ep->regs, MUSB_TXCSR);
txcsr |= MGC_M_TXCSR_DMAENAB | MGC_M_TXCSR_H_WZC_BITS;
- musb_writew(ep->regs, MGC_O_HDRC_TXCSR, txcsr);
+ musb_writew(ep->regs, MUSB_TXCSR, txcsr);
}
/*
case USB_ENDPOINT_XFER_INT:
DBG(3, "check whether there's still time for periodic Tx\n");
qh->iso_idx = 0;
- wFrame = musb_readw(mbase, MGC_O_HDRC_FRAME);
+ wFrame = musb_readw(mbase, MUSB_FRAME);
/* FIXME this doesn't implement that scheduling policy ...
* or handle framecounter wrapping
*/
/* enable SOF interrupt so we can count down */
DBG(1,"SOF for %d\n", epnum);
#if 1 // ifndef CONFIG_ARCH_DAVINCI
- musb_writeb(mbase, MGC_O_HDRC_INTRUSBE, 0xff);
+ musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
#endif
}
break;
qh = ep->out_qh;
if (!is_in) {
- csr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ csr = musb_readw(epio, MUSB_TXCSR);
usb_settoggle(udev, qh->epnum, 1,
(csr & MGC_M_TXCSR_H_DATATOGGLE)
? 1 : 0);
} else {
- csr = musb_readw(epio, MGC_O_HDRC_RXCSR);
+ csr = musb_readw(epio, MUSB_RXCSR);
usb_settoggle(udev, qh->epnum, 0,
(csr & MGC_M_RXCSR_H_DATATOGGLE)
? 1 : 0);
);
/* write 2x to allow double buffering */
- musb_writew(hw_ep->regs, MGC_O_HDRC_RXCSR, csr);
- musb_writew(hw_ep->regs, MGC_O_HDRC_RXCSR, csr);
+ musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
+ musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
/* flush writebuffer */
- return musb_readw(hw_ep->regs, MGC_O_HDRC_RXCSR);
+ return musb_readw(hw_ep->regs, MUSB_RXCSR);
}
/*
void *buffer = pUrb->transfer_buffer;
// musb_ep_select(mbase, epnum);
- wRxCount = musb_readw(epio, MGC_O_HDRC_RXCOUNT);
+ wRxCount = musb_readw(epio, MUSB_RXCOUNT);
DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, wRxCount,
pUrb->transfer_buffer, qh->offset,
pUrb->transfer_buffer_length);
musb_read_fifo(hw_ep, length, pBuffer);
- wCsr = musb_readw(epio, MGC_O_HDRC_RXCSR);
+ wCsr = musb_readw(epio, MUSB_RXCSR);
wCsr |= MGC_M_RXCSR_H_WZC_BITS;
if (unlikely(do_flush))
musb_h_flush_rxfifo(hw_ep, wCsr);
wCsr &= ~(MGC_M_RXCSR_RXPKTRDY | MGC_M_RXCSR_H_REQPKT);
if (!bDone)
wCsr |= MGC_M_RXCSR_H_REQPKT;
- musb_writew(epio, MGC_O_HDRC_RXCSR, wCsr);
+ musb_writew(epio, MUSB_RXCSR, wCsr);
}
return bDone;
/* if programmed for Tx, put it in RX mode */
if (ep->is_shared_fifo) {
- csr = musb_readw(ep->regs, MGC_O_HDRC_TXCSR);
+ csr = musb_readw(ep->regs, MUSB_TXCSR);
if (csr & MGC_M_TXCSR_MODE) {
musb_h_tx_flush_fifo(ep);
- musb_writew(ep->regs, MGC_O_HDRC_TXCSR,
+ musb_writew(ep->regs, MUSB_TXCSR,
MGC_M_TXCSR_FRCDATATOG);
}
/* clear mode (and everything else) to enable Rx */
- musb_writew(ep->regs, MGC_O_HDRC_TXCSR, 0);
+ musb_writew(ep->regs, MUSB_TXCSR, 0);
/* scrub all previous state, clearing toggle */
} else {
- csr = musb_readw(ep->regs, MGC_O_HDRC_RXCSR);
+ csr = musb_readw(ep->regs, MUSB_RXCSR);
if (csr & MGC_M_RXCSR_RXPKTRDY)
WARN("rx%d, packet/%d ready?\n", ep->epnum,
- musb_readw(ep->regs, MGC_O_HDRC_RXCOUNT));
+ musb_readw(ep->regs, MUSB_RXCOUNT));
musb_h_flush_rxfifo(ep, MGC_M_RXCSR_CLRDATATOG);
}
/* target addr and (for multipoint) hub addr/port */
if (musb->is_multipoint) {
- musb_writeb(ep->target_regs, MGC_O_HDRC_RXFUNCADDR,
+ musb_writeb(ep->target_regs, MUSB_RXFUNCADDR,
qh->addr_reg);
- musb_writeb(ep->target_regs, MGC_O_HDRC_RXHUBADDR,
+ musb_writeb(ep->target_regs, MUSB_RXHUBADDR,
qh->h_addr_reg);
- musb_writeb(ep->target_regs, MGC_O_HDRC_RXHUBPORT,
+ musb_writeb(ep->target_regs, MUSB_RXHUBPORT,
qh->h_port_reg);
} else
- musb_writeb(musb->mregs, MGC_O_HDRC_FADDR, qh->addr_reg);
+ musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
/* protocol/endpoint, interval/NAKlimit, i/o size */
- musb_writeb(ep->regs, MGC_O_HDRC_RXTYPE, qh->type_reg);
- musb_writeb(ep->regs, MGC_O_HDRC_RXINTERVAL, qh->intv_reg);
+ musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
+ musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
/* NOTE: bulk combining rewrites high bits of maxpacket */
- musb_writew(ep->regs, MGC_O_HDRC_RXMAXP, qh->maxpacket);
+ musb_writew(ep->regs, MUSB_RXMAXP, qh->maxpacket);
ep->rx_reinit = 0;
}
u16 wIntrTxE;
u16 wLoadCount;
- wCsr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ wCsr = musb_readw(epio, MUSB_TXCSR);
/* disable interrupt in case we flush */
- wIntrTxE = musb_readw(mbase, MGC_O_HDRC_INTRTXE);
- musb_writew(mbase, MGC_O_HDRC_INTRTXE, wIntrTxE & ~(1 << epnum));
+ wIntrTxE = musb_readw(mbase, MUSB_INTRTXE);
+ musb_writew(mbase, MUSB_INTRTXE, wIntrTxE & ~(1 << epnum));
/* general endpoint setup */
if (epnum) {
csr |= MGC_M_TXCSR_CLRDATATOG;
/* twice in case of double packet buffering */
- musb_writew(epio, MGC_O_HDRC_TXCSR, csr);
+ musb_writew(epio, MUSB_TXCSR, csr);
/* REVISIT may need to clear FLUSHFIFO ... */
- musb_writew(epio, MGC_O_HDRC_TXCSR, csr);
- wCsr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ musb_writew(epio, MUSB_TXCSR, csr);
+ wCsr = musb_readw(epio, MUSB_TXCSR);
} else {
/* endpoint 0: just flush */
- musb_writew(epio, MGC_O_HDRC_CSR0,
+ musb_writew(epio, MUSB_CSR0,
wCsr | MGC_M_CSR0_FLUSHFIFO);
- musb_writew(epio, MGC_O_HDRC_CSR0,
+ musb_writew(epio, MUSB_CSR0,
wCsr | MGC_M_CSR0_FLUSHFIFO);
}
/* target addr and (for multipoint) hub addr/port */
if (musb->is_multipoint) {
musb_writeb(mbase,
- MGC_BUSCTL_OFFSET(epnum, MGC_O_HDRC_TXFUNCADDR),
+ MGC_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
qh->addr_reg);
musb_writeb(mbase,
- MGC_BUSCTL_OFFSET(epnum, MGC_O_HDRC_TXHUBADDR),
+ MGC_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
qh->h_addr_reg);
musb_writeb(mbase,
- MGC_BUSCTL_OFFSET(epnum, MGC_O_HDRC_TXHUBPORT),
+ MGC_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
qh->h_port_reg);
/* FIXME if !epnum, do the same for RX ... */
} else
- musb_writeb(mbase, MGC_O_HDRC_FADDR, qh->addr_reg);
+ musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
/* protocol/endpoint/interval/NAKlimit */
if (epnum) {
- musb_writeb(epio, MGC_O_HDRC_TXTYPE, qh->type_reg);
+ musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
if (can_bulk_split(musb, qh->type))
- musb_writew(epio, MGC_O_HDRC_TXMAXP,
+ musb_writew(epio, MUSB_TXMAXP,
packet_sz
| ((hw_ep->max_packet_sz_tx /
packet_sz) - 1) << 11);
else
- musb_writew(epio, MGC_O_HDRC_TXMAXP,
+ musb_writew(epio, MUSB_TXMAXP,
packet_sz);
- musb_writeb(epio, MGC_O_HDRC_TXINTERVAL, qh->intv_reg);
+ musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
} else {
- musb_writeb(epio, MGC_O_HDRC_NAKLIMIT0, qh->intv_reg);
+ musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
if (musb->is_multipoint)
- musb_writeb(epio, MGC_O_HDRC_TYPE0,
+ musb_writeb(epio, MUSB_TYPE0,
qh->type_reg);
}
if (pDmaChannel) {
/* clear previous state */
- wCsr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ wCsr = musb_readw(epio, MUSB_TXCSR);
wCsr &= ~(MGC_M_TXCSR_AUTOSET
| MGC_M_TXCSR_DMAMODE
| MGC_M_TXCSR_DMAENAB);
wCsr |= MGC_M_TXCSR_MODE;
- musb_writew(epio, MGC_O_HDRC_TXCSR,
+ musb_writew(epio, MUSB_TXCSR,
wCsr | MGC_M_TXCSR_MODE);
qh->segsize = min(dwLength, pDmaChannel->max_len);
| MGC_M_TXCSR_DMAENAB
| MGC_M_TXCSR_DMAMODE);
- musb_writew(epio, MGC_O_HDRC_TXCSR, wCsr);
+ musb_writew(epio, MUSB_TXCSR, wCsr);
bDmaOk = dma_controller->channel_program(
pDmaChannel, packet_sz,
* assume CPPI setup succeeds.
* defer enabling dma.
*/
- wCsr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ wCsr = musb_readw(epio, MUSB_TXCSR);
wCsr &= ~(MGC_M_TXCSR_AUTOSET
| MGC_M_TXCSR_DMAMODE
| MGC_M_TXCSR_DMAENAB);
wCsr |= MGC_M_TXCSR_MODE;
- musb_writew(epio, MGC_O_HDRC_TXCSR,
+ musb_writew(epio, MUSB_TXCSR,
wCsr | MGC_M_TXCSR_MODE);
pDmaChannel->actual_len = 0L;
/* PIO to load FIFO */
qh->segsize = wLoadCount;
musb_write_fifo(hw_ep, wLoadCount, pBuffer);
- wCsr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ wCsr = musb_readw(epio, MUSB_TXCSR);
wCsr &= ~(MGC_M_TXCSR_DMAENAB
| MGC_M_TXCSR_DMAMODE
| MGC_M_TXCSR_AUTOSET);
wCsr |= MGC_M_TXCSR_MODE;
if (epnum)
- musb_writew(epio, MGC_O_HDRC_TXCSR, wCsr);
+ musb_writew(epio, MUSB_TXCSR, wCsr);
}
/* re-enable interrupt */
- musb_writew(mbase, MGC_O_HDRC_INTRTXE, wIntrTxE);
+ musb_writew(mbase, MUSB_INTRTXE, wIntrTxE);
/* IN/receive */
} else {
csr |= MGC_M_RXCSR_DISNYET;
} else {
- csr = musb_readw(hw_ep->regs, MGC_O_HDRC_RXCSR);
+ csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
if (csr & (MGC_M_RXCSR_RXPKTRDY
| MGC_M_RXCSR_DMAENAB
qh->segsize = dwLength;
/* AUTOREQ is in a DMA register */
- musb_writew(hw_ep->regs, MGC_O_HDRC_RXCSR, csr);
+ musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
csr = musb_readw(hw_ep->regs,
- MGC_O_HDRC_RXCSR);
+ MUSB_RXCSR);
/* unless caller treats short rx transfers as
* errors, we dare not queue multiple transfers.
csr |= MGC_M_RXCSR_H_REQPKT;
DBG(7, "RXCSR%d := %04x\n", epnum, csr);
- musb_writew(hw_ep->regs, MGC_O_HDRC_RXCSR, csr);
- csr = musb_readw(hw_ep->regs, MGC_O_HDRC_RXCSR);
+ musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
+ csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
}
}
pUrb = next_urb(qh);
musb_ep_select(mbase, 0);
- csr = musb_readw(epio, MGC_O_HDRC_CSR0);
+ csr = musb_readw(epio, MUSB_CSR0);
len = (csr & MGC_M_CSR0_RXPKTRDY)
- ? musb_readb(epio, MGC_O_HDRC_COUNT0)
+ ? musb_readb(epio, MUSB_COUNT0)
: 0;
DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
* if (qh->ring.next != &musb->control), then
* we have a candidate... NAKing is *NOT* an error
*/
- musb_writew(epio, MGC_O_HDRC_CSR0, 0);
+ musb_writew(epio, MUSB_CSR0, 0);
retval = IRQ_HANDLED;
}
/* use the proper sequence to abort the transfer */
if (csr & MGC_M_CSR0_H_REQPKT) {
csr &= ~MGC_M_CSR0_H_REQPKT;
- musb_writew(epio, MGC_O_HDRC_CSR0, csr);
+ musb_writew(epio, MUSB_CSR0, csr);
csr &= ~MGC_M_CSR0_H_NAKTIMEOUT;
- musb_writew(epio, MGC_O_HDRC_CSR0, csr);
+ musb_writew(epio, MUSB_CSR0, csr);
} else {
csr |= MGC_M_CSR0_FLUSHFIFO;
- musb_writew(epio, MGC_O_HDRC_CSR0, csr);
- musb_writew(epio, MGC_O_HDRC_CSR0, csr);
+ musb_writew(epio, MUSB_CSR0, csr);
+ musb_writew(epio, MUSB_CSR0, csr);
csr &= ~MGC_M_CSR0_H_NAKTIMEOUT;
- musb_writew(epio, MGC_O_HDRC_CSR0, csr);
+ musb_writew(epio, MUSB_CSR0, csr);
}
- musb_writeb(epio, MGC_O_HDRC_NAKLIMIT0, 0);
+ musb_writeb(epio, MUSB_NAKLIMIT0, 0);
/* clear it */
- musb_writew(epio, MGC_O_HDRC_CSR0, 0);
+ musb_writew(epio, MUSB_CSR0, 0);
}
if (unlikely(!pUrb)) {
* SHOULD NEVER HAPPEN! */
ERR("no URB for end 0\n");
- musb_writew(epio, MGC_O_HDRC_CSR0, MGC_M_CSR0_FLUSHFIFO);
- musb_writew(epio, MGC_O_HDRC_CSR0, MGC_M_CSR0_FLUSHFIFO);
- musb_writew(epio, MGC_O_HDRC_CSR0, 0);
+ musb_writew(epio, MUSB_CSR0, MGC_M_CSR0_FLUSHFIFO);
+ musb_writew(epio, MUSB_CSR0, MGC_M_CSR0_FLUSHFIFO);
+ musb_writew(epio, MUSB_CSR0, 0);
goto done;
}
DBG(5, "ep0 STATUS, csr %04x\n", csr);
}
- musb_writew(epio, MGC_O_HDRC_CSR0, csr);
+ musb_writew(epio, MUSB_CSR0, csr);
retval = IRQ_HANDLED;
} else
musb->ep0_stage = MGC_END0_IDLE;
pUrb = next_urb(qh);
musb_ep_select(mbase, epnum);
- wTxCsrVal = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ wTxCsrVal = musb_readw(epio, MUSB_TXCSR);
/* with CPPI, DMA sometimes triggers "extra" irqs */
if (!pUrb) {
* we have a candidate... NAKing is *NOT* an error
*/
musb_ep_select(mbase, epnum);
- musb_writew(epio, MGC_O_HDRC_CSR0,
+ musb_writew(epio, MUSB_CSR0,
MGC_M_TXCSR_H_WZC_BITS
| MGC_M_TXCSR_TXPKTRDY);
goto finish;
);
musb_ep_select(mbase, epnum);
- musb_writew(epio, MGC_O_HDRC_TXCSR, wTxCsrVal);
+ musb_writew(epio, MUSB_TXCSR, wTxCsrVal);
/* REVISIT may need to clear FLUSHFIFO ... */
- musb_writew(epio, MGC_O_HDRC_TXCSR, wTxCsrVal);
- musb_writeb(epio, MGC_O_HDRC_TXINTERVAL, 0);
+ musb_writew(epio, MUSB_TXCSR, wTxCsrVal);
+ musb_writeb(epio, MUSB_TXINTERVAL, 0);
bDone = TRUE;
}
qh->segsize = wLength;
musb_ep_select(mbase, epnum);
- musb_writew(epio, MGC_O_HDRC_TXCSR,
+ musb_writew(epio, MUSB_TXCSR,
MGC_M_TXCSR_H_WZC_BITS | MGC_M_TXCSR_TXPKTRDY);
} else
DBG(1, "not complete, but dma enabled?\n");
status = 0;
xfer_len = 0;
- wVal = wRxCsrVal = musb_readw(epio, MGC_O_HDRC_RXCSR);
+ wVal = wRxCsrVal = musb_readw(epio, MUSB_RXCSR);
if (unlikely(!pUrb)) {
/* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
* with fifo full. (Only with DMA??)
*/
DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, wVal,
- musb_readw(epio, MGC_O_HDRC_RXCOUNT));
+ musb_readw(epio, MUSB_RXCOUNT));
musb_h_flush_rxfifo(hw_ep, MGC_M_RXCSR_CLRDATATOG);
return;
}
DBG(3, "end %d RX proto error\n", epnum);
status = -EPROTO;
- musb_writeb(epio, MGC_O_HDRC_RXINTERVAL, 0);
+ musb_writeb(epio, MUSB_RXINTERVAL, 0);
} else if (wRxCsrVal & MGC_M_RXCSR_DATAERROR) {
*/
DBG(6, "RX end %d NAK timeout\n", epnum);
musb_ep_select(mbase, epnum);
- musb_writew(epio, MGC_O_HDRC_RXCSR,
+ musb_writew(epio, MUSB_RXCSR,
MGC_M_RXCSR_H_WZC_BITS
| MGC_M_RXCSR_H_REQPKT);
xfer_len = dma->actual_len;
}
musb_h_flush_rxfifo(hw_ep, 0);
- musb_writeb(epio, MGC_O_HDRC_RXINTERVAL, 0);
+ musb_writeb(epio, MUSB_RXINTERVAL, 0);
bDone = TRUE;
goto finish;
}
wRxCsrVal &= ~MGC_M_RXCSR_H_REQPKT;
musb_ep_select(mbase, epnum);
- musb_writew(epio, MGC_O_HDRC_RXCSR,
+ musb_writew(epio, MUSB_RXCSR,
MGC_M_RXCSR_H_WZC_BITS | wRxCsrVal);
}
#endif
| MGC_M_RXCSR_H_AUTOREQ
| MGC_M_RXCSR_AUTOCLEAR
| MGC_M_RXCSR_RXPKTRDY);
- musb_writew(hw_ep->regs, MGC_O_HDRC_RXCSR, wVal);
+ musb_writew(hw_ep->regs, MUSB_RXCSR, wVal);
#ifdef CONFIG_USB_INVENTRA_DMA
/* bDone if pUrb buffer is full or short packet is recd */
/* send IN token for next packet, without AUTOREQ */
if (!bDone) {
wVal |= MGC_M_RXCSR_H_REQPKT;
- musb_writew(epio, MGC_O_HDRC_RXCSR,
+ musb_writew(epio, MUSB_RXCSR,
MGC_M_RXCSR_H_WZC_BITS | wVal);
}
DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
bDone ? "off" : "reset",
- musb_readw(epio, MGC_O_HDRC_RXCSR),
- musb_readw(epio, MGC_O_HDRC_RXCOUNT));
+ musb_readw(epio, MUSB_RXCSR),
+ musb_readw(epio, MUSB_RXCOUNT));
#else
bDone = TRUE;
#endif
/* do the proper sequence to abort the transfer */
musb_ep_select(mbase, epnum);
wVal &= ~MGC_M_RXCSR_H_REQPKT;
- musb_writew(epio, MGC_O_HDRC_RXCSR, wVal);
+ musb_writew(epio, MUSB_RXCSR, wVal);
goto finish;
}
u16 wRxCount;
int status;
- wRxCount = musb_readw(epio, MGC_O_HDRC_RXCOUNT);
+ wRxCount = musb_readw(epio, MUSB_RXCOUNT);
DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
epnum, wRxCount,
* wait for an interrupt when the pkt is recd. Well, you won't get any!
*/
- wVal = musb_readw(epio, MGC_O_HDRC_RXCSR);
+ wVal = musb_readw(epio, MUSB_RXCSR);
wVal &= ~MGC_M_RXCSR_H_REQPKT;
if (dma->desired_mode == 0)
wVal |= MGC_M_RXCSR_H_AUTOREQ;
wVal |= MGC_M_RXCSR_AUTOCLEAR | MGC_M_RXCSR_DMAENAB;
- musb_writew(epio, MGC_O_HDRC_RXCSR,
+ musb_writew(epio, MUSB_RXCSR,
MGC_M_RXCSR_H_WZC_BITS | wVal);
/* REVISIT if when actual_length != 0,
*/
} else {
musb_h_tx_flush_fifo(ep);
- csr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ csr = musb_readw(epio, MUSB_TXCSR);
csr &= ~( MGC_M_TXCSR_AUTOSET
| MGC_M_TXCSR_DMAENAB
| MGC_M_TXCSR_H_RXSTALL
| MGC_M_TXCSR_H_ERROR
| MGC_M_TXCSR_TXPKTRDY
);
- musb_writew(epio, MGC_O_HDRC_TXCSR, csr);
+ musb_writew(epio, MUSB_TXCSR, csr);
/* REVISIT may need to clear FLUSHFIFO ... */
- musb_writew(epio, MGC_O_HDRC_TXCSR, csr);
+ musb_writew(epio, MUSB_TXCSR, csr);
/* flush cpu writebuffer */
- csr = musb_readw(epio, MGC_O_HDRC_TXCSR);
+ csr = musb_readw(epio, MUSB_TXCSR);
}
if (status == 0)
musb_advance_schedule(ep->musb, urb, ep, is_in);
{
struct musb *musb = hcd_to_musb(hcd);
- return musb_readw(musb->mregs, MGC_O_HDRC_FRAME);
+ return musb_readw(musb->mregs, MUSB_FRAME);
}
static int musb_h_start(struct usb_hcd *hcd)
mode, ep->dma ? " dma" : "",
musb_readw(regs,
(ep->is_in || !ep->current_epnum)
- ? MGC_O_HDRC_TXCSR
- : MGC_O_HDRC_RXCSR),
+ ? MUSB_TXCSR
+ : MUSB_RXCSR),
musb_readw(regs, ep->is_in
- ? MGC_O_HDRC_TXMAXP
- : MGC_O_HDRC_RXMAXP)
+ ? MUSB_TXMAXP
+ : MUSB_RXMAXP)
);
if (code <= 0)
break;
epnum,
hw_ep->rx_double_buffered
? "2buf" : "1buf",
- musb_readw(regs, MGC_O_HDRC_RXCSR),
- musb_readb(regs, MGC_O_HDRC_RXINTERVAL),
- musb_readw(regs, MGC_O_HDRC_RXMAXP),
- musb_readb(regs, MGC_O_HDRC_RXTYPE),
+ musb_readw(regs, MUSB_RXCSR),
+ musb_readb(regs, MUSB_RXINTERVAL),
+ musb_readw(regs, MUSB_RXMAXP),
+ musb_readb(regs, MUSB_RXTYPE),
/* FIXME: assumes multipoint */
musb_readb(musb->mregs,
MGC_BUSCTL_OFFSET(epnum,
- MGC_O_HDRC_RXFUNCADDR)),
+ MUSB_RXFUNCADDR)),
musb_readb(musb->mregs,
MGC_BUSCTL_OFFSET(epnum,
- MGC_O_HDRC_RXHUBADDR)),
+ MUSB_RXHUBADDR)),
musb_readb(musb->mregs,
MGC_BUSCTL_OFFSET(epnum,
- MGC_O_HDRC_RXHUBPORT))
+ MUSB_RXHUBPORT))
);
if (code <= 0)
break;
epnum,
hw_ep->tx_double_buffered
? "2buf" : "1buf",
- musb_readw(regs, MGC_O_HDRC_TXCSR),
- musb_readb(regs, MGC_O_HDRC_TXINTERVAL),
- musb_readw(regs, MGC_O_HDRC_TXMAXP),
- musb_readb(regs, MGC_O_HDRC_TXTYPE),
+ musb_readw(regs, MUSB_TXCSR),
+ musb_readb(regs, MUSB_TXINTERVAL),
+ musb_readw(regs, MUSB_TXMAXP),
+ musb_readb(regs, MUSB_TXTYPE),
/* FIXME: assumes multipoint */
musb_readb(musb->mregs,
MGC_BUSCTL_OFFSET(epnum,
- MGC_O_HDRC_TXFUNCADDR)),
+ MUSB_TXFUNCADDR)),
musb_readb(musb->mregs,
MGC_BUSCTL_OFFSET(epnum,
- MGC_O_HDRC_TXHUBADDR)),
+ MUSB_TXHUBADDR)),
musb_readb(musb->mregs,
MGC_BUSCTL_OFFSET(epnum,
- MGC_O_HDRC_TXHUBPORT))
+ MUSB_TXHUBPORT))
);
if (code <= 0)
break;
count = sprintf(buffer, "Status: %sHDRC, Mode=%s "
"(Power=%02x, DevCtl=%02x)\n",
(musb->is_multipoint ? "M" : ""), MUSB_MODE(musb),
- musb_readb(mbase, MGC_O_HDRC_POWER),
- musb_readb(mbase, MGC_O_HDRC_DEVCTL));
+ musb_readb(mbase, MUSB_POWER),
+ musb_readb(mbase, MUSB_DEVCTL));
if (count <= 0)
return 0;
buffer += count;
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
code = sprintf(buffer, "Peripheral address: %02x\n",
- musb_readb(musb, MGC_O_HDRC_FADDR));
+ musb_readb(musb, MUSB_FADDR));
if (code <= 0)
goto done;
buffer += code;
switch (cmd) {
case 'C':
if (mbase) {
- bReg = musb_readb(mbase, MGC_O_HDRC_POWER)
+ bReg = musb_readb(mbase, MUSB_POWER)
| MGC_M_POWER_SOFTCONN;
- musb_writeb(mbase, MGC_O_HDRC_POWER, bReg);
+ musb_writeb(mbase, MUSB_POWER, bReg);
}
break;
case 'c':
if (mbase) {
- bReg = musb_readb(mbase, MGC_O_HDRC_POWER)
+ bReg = musb_readb(mbase, MUSB_POWER)
& ~MGC_M_POWER_SOFTCONN;
- musb_writeb(mbase, MGC_O_HDRC_POWER, bReg);
+ musb_writeb(mbase, MUSB_POWER, bReg);
}
break;
case 'I':
if (mbase) {
- bReg = musb_readb(mbase, MGC_O_HDRC_POWER)
+ bReg = musb_readb(mbase, MUSB_POWER)
| MGC_M_POWER_HSENAB;
- musb_writeb(mbase, MGC_O_HDRC_POWER, bReg);
+ musb_writeb(mbase, MUSB_POWER, bReg);
}
break;
case 'i':
if (mbase) {
- bReg = musb_readb(mbase, MGC_O_HDRC_POWER)
+ bReg = musb_readb(mbase, MUSB_POWER)
& ~MGC_M_POWER_HSENAB;
- musb_writeb(mbase, MGC_O_HDRC_POWER, bReg);
+ musb_writeb(mbase, MUSB_POWER, bReg);
}
break;
case 'F':
- bReg = musb_readb(mbase, MGC_O_HDRC_DEVCTL);
+ bReg = musb_readb(mbase, MUSB_DEVCTL);
bReg |= MGC_M_DEVCTL_SESSION;
- musb_writeb(mbase, MGC_O_HDRC_DEVCTL, bReg);
+ musb_writeb(mbase, MUSB_DEVCTL, bReg);
break;
case 'H':
if (mbase) {
- bReg = musb_readb(mbase, MGC_O_HDRC_DEVCTL);
+ bReg = musb_readb(mbase, MUSB_DEVCTL);
bReg |= MGC_M_DEVCTL_HR;
- musb_writeb(mbase, MGC_O_HDRC_DEVCTL, bReg);
+ musb_writeb(mbase, MUSB_DEVCTL, bReg);
//MUSB_HST_MODE( ((struct musb*)data) );
//WARN("Host Mode\n");
}
case 'h':
if (mbase) {
- bReg = musb_readb(mbase, MGC_O_HDRC_DEVCTL);
+ bReg = musb_readb(mbase, MUSB_DEVCTL);
bReg &= ~MGC_M_DEVCTL_HR;
- musb_writeb(mbase, MGC_O_HDRC_DEVCTL, bReg);
+ musb_writeb(mbase, MUSB_DEVCTL, bReg);
}
break;
case 'T':
if (mbase) {
musb_load_testpacket(musb);
- musb_writeb(mbase, MGC_O_HDRC_TESTMODE,
+ musb_writeb(mbase, MUSB_TESTMODE,
MGC_M_TEST_PACKET);
}
break;
/* TUSB mapping: "flat" plus ep0 special cases */
#if defined(CONFIG_USB_TUSB6010)
#define musb_ep_select(_mbase, _epnum) \
- musb_writeb((_mbase), MGC_O_HDRC_INDEX, (_epnum))
+ musb_writeb((_mbase), MUSB_INDEX, (_epnum))
#define MGC_END_OFFSET MGC_TUSB_OFFSET
/* "flat" mapping: each endpoint has its own i/o address */
/* "indexed" mapping: INDEX register controls register bank select */
#else
#define musb_ep_select(_mbase, _epnum) \
- musb_writeb((_mbase), MGC_O_HDRC_INDEX, (_epnum))
+ musb_writeb((_mbase), MUSB_INDEX, (_epnum))
#define MGC_END_OFFSET MGC_INDEXED_OFFSET
#endif
{ (_musb)->is_host=FALSE; }
#define test_devctl_hst_mode(_x) \
- (musb_readb((_x)->mregs, MGC_O_HDRC_DEVCTL)&MGC_M_DEVCTL_HM)
+ (musb_readb((_x)->mregs, MUSB_DEVCTL)&MGC_M_DEVCTL_HM)
#define MUSB_MODE(musb) ((musb)->is_host ? "Host" : "Peripheral")
/* Common USB registers */
-#define MGC_O_HDRC_FADDR 0x00 /* 8-bit */
-#define MGC_O_HDRC_POWER 0x01 /* 8-bit */
-
-#define MGC_O_HDRC_INTRTX 0x02 /* 16-bit */
-#define MGC_O_HDRC_INTRRX 0x04
-#define MGC_O_HDRC_INTRTXE 0x06
-#define MGC_O_HDRC_INTRRXE 0x08
-#define MGC_O_HDRC_INTRUSB 0x0A /* 8 bit */
-#define MGC_O_HDRC_INTRUSBE 0x0B /* 8 bit */
-#define MGC_O_HDRC_FRAME 0x0C
-#define MGC_O_HDRC_INDEX 0x0E /* 8 bit */
-#define MGC_O_HDRC_TESTMODE 0x0F /* 8 bit */
+#define MUSB_FADDR 0x00 /* 8-bit */
+#define MUSB_POWER 0x01 /* 8-bit */
+
+#define MUSB_INTRTX 0x02 /* 16-bit */
+#define MUSB_INTRRX 0x04
+#define MUSB_INTRTXE 0x06
+#define MUSB_INTRRXE 0x08
+#define MUSB_INTRUSB 0x0A /* 8 bit */
+#define MUSB_INTRUSBE 0x0B /* 8 bit */
+#define MUSB_FRAME 0x0C
+#define MUSB_INDEX 0x0E /* 8 bit */
+#define MUSB_TESTMODE 0x0F /* 8 bit */
/* Get offset for a given FIFO from musb->mregs */
#ifdef CONFIG_USB_TUSB6010
/* Additional Control Registers */
-#define MGC_O_HDRC_DEVCTL 0x60 /* 8 bit */
+#define MUSB_DEVCTL 0x60 /* 8 bit */
/* These are always controlled through the INDEX register */
-#define MGC_O_HDRC_TXFIFOSZ 0x62 /* 8-bit (see masks) */
-#define MGC_O_HDRC_RXFIFOSZ 0x63 /* 8-bit (see masks) */
-#define MGC_O_HDRC_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
-#define MGC_O_HDRC_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
+#define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
+#define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
+#define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
+#define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
// vctrl/vstatus: optional vendor utmi+phy register at 0x68
-#define MGC_O_HDRC_HWVERS 0x6C /* 8 bit */
+#define MUSB_HWVERS 0x6C /* 8 bit */
-#define MGC_O_HDRC_EPINFO 0x78 /* 8 bit */
-#define MGC_O_HDRC_RAMINFO 0x79 /* 8 bit */
-#define MGC_O_HDRC_LINKINFO 0x7a /* 8 bit */
-#define MGC_O_HDRC_VPLEN 0x7b /* 8 bit */
-#define MGC_O_HDRC_HS_EOF1 0x7c /* 8 bit */
-#define MGC_O_HDRC_FS_EOF1 0x7d /* 8 bit */
-#define MGC_O_HDRC_LS_EOF1 0x7e /* 8 bit */
+#define MUSB_EPINFO 0x78 /* 8 bit */
+#define MUSB_RAMINFO 0x79 /* 8 bit */
+#define MUSB_LINKINFO 0x7a /* 8 bit */
+#define MUSB_VPLEN 0x7b /* 8 bit */
+#define MUSB_HS_EOF1 0x7c /* 8 bit */
+#define MUSB_FS_EOF1 0x7d /* 8 bit */
+#define MUSB_LS_EOF1 0x7e /* 8 bit */
/* offsets to endpoint registers */
-#define MGC_O_HDRC_TXMAXP 0x00
-#define MGC_O_HDRC_TXCSR 0x02
-#define MGC_O_HDRC_CSR0 MGC_O_HDRC_TXCSR /* re-used for EP0 */
-#define MGC_O_HDRC_RXMAXP 0x04
-#define MGC_O_HDRC_RXCSR 0x06
-#define MGC_O_HDRC_RXCOUNT 0x08
-#define MGC_O_HDRC_COUNT0 MGC_O_HDRC_RXCOUNT /* re-used for EP0 */
-#define MGC_O_HDRC_TXTYPE 0x0A
-#define MGC_O_HDRC_TYPE0 MGC_O_HDRC_TXTYPE /* re-used for EP0 */
-#define MGC_O_HDRC_TXINTERVAL 0x0B
-#define MGC_O_HDRC_NAKLIMIT0 MGC_O_HDRC_TXINTERVAL /* re-used for EP0 */
-#define MGC_O_HDRC_RXTYPE 0x0C
-#define MGC_O_HDRC_RXINTERVAL 0x0D
-#define MGC_O_HDRC_FIFOSIZE 0x0F
-#define MGC_O_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
+#define MUSB_TXMAXP 0x00
+#define MUSB_TXCSR 0x02
+#define MUSB_CSR0 MUSB_TXCSR /* re-used for EP0 */
+#define MUSB_RXMAXP 0x04
+#define MUSB_RXCSR 0x06
+#define MUSB_RXCOUNT 0x08
+#define MUSB_COUNT0 MUSB_RXCOUNT /* re-used for EP0 */
+#define MUSB_TXTYPE 0x0A
+#define MUSB_TYPE0 MUSB_TXTYPE /* re-used for EP0 */
+#define MUSB_TXINTERVAL 0x0B
+#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* re-used for EP0 */
+#define MUSB_RXTYPE 0x0C
+#define MUSB_RXINTERVAL 0x0D
+#define MUSB_FIFOSIZE 0x0F
+#define MUSB_CONFIGDATA MUSB_FIFOSIZE /* re-used for EP0 */
/* offsets to endpoint registers in indexed model (using INDEX register) */
#define MGC_INDEXED_OFFSET(_epnum, _bOffset) \
#endif
/* "bus control"/target registers, for host side multipoint (external hubs) */
-#define MGC_O_HDRC_TXFUNCADDR 0x00
-#define MGC_O_HDRC_TXHUBADDR 0x02
-#define MGC_O_HDRC_TXHUBPORT 0x03
+#define MUSB_TXFUNCADDR 0x00
+#define MUSB_TXHUBADDR 0x02
+#define MUSB_TXHUBPORT 0x03
-#define MGC_O_HDRC_RXFUNCADDR 0x04
-#define MGC_O_HDRC_RXHUBADDR 0x06
-#define MGC_O_HDRC_RXHUBPORT 0x07
+#define MUSB_RXFUNCADDR 0x04
+#define MUSB_RXHUBADDR 0x06
+#define MUSB_RXHUBPORT 0x07
#define MGC_BUSCTL_OFFSET(_epnum, _bOffset) \
(0x80 + (8*(_epnum)) + (_bOffset))
if (pImplChannel->bTransmit) {
csr = musb_readw(mbase,
- MGC_END_OFFSET(pImplChannel->epnum,MGC_O_HDRC_TXCSR));
+ MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR));
csr &= ~(MGC_M_TXCSR_AUTOSET |
MGC_M_TXCSR_DMAENAB |
MGC_M_TXCSR_DMAMODE);
musb_writew(mbase,
- MGC_END_OFFSET(pImplChannel->epnum,MGC_O_HDRC_TXCSR),
+ MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
csr);
}
else {
csr = musb_readw(mbase,
- MGC_END_OFFSET(pImplChannel->epnum,MGC_O_HDRC_RXCSR));
+ MGC_END_OFFSET(pImplChannel->epnum,MUSB_RXCSR));
csr &= ~(MGC_M_RXCSR_AUTOCLEAR |
MGC_M_RXCSR_DMAENAB |
MGC_M_RXCSR_DMAMODE);
musb_writew(mbase,
- MGC_END_OFFSET(pImplChannel->epnum,MGC_O_HDRC_RXCSR),
+ MGC_END_OFFSET(pImplChannel->epnum,MUSB_RXCSR),
csr);
}
"=> reconfig 0": "=> complete");
u8 devctl = musb_readb(mbase,
- MGC_O_HDRC_DEVCTL);
+ MUSB_DEVCTL);
pChannel->status = MGC_DMA_STATUS_FREE;
musb_ep_select(mbase,
pImplChannel->epnum);
musb_writew(mbase,
- MGC_END_OFFSET(pImplChannel->epnum,MGC_O_HDRC_TXCSR),
+ MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
MGC_M_TXCSR_TXPKTRDY);
} else
musb_dma_completion(
* that must be ignored.
*/
- devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
if (is_on) {
musb->is_active = 1;
MUSB_DEV_MODE(musb);
}
- musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, devctl);
+ musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
DBG(1, "VBUS %s, devctl %02x "
/* otg %3x conf %08x prcm %08x */ "\n",
otg_state_string(musb),
- musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL));
+ musb_readb(musb->mregs, MUSB_DEVCTL));
}
static int omap_set_power(struct otg_transceiver *x, unsigned mA)
{
musb_ep_select(musb->mregs, 0);
musb_write_fifo(musb->control_ep,
sizeof(musb_test_packet), musb_test_packet);
- musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_TXPKTRDY);
+ musb_writew(regs, MUSB_CSR0, MGC_M_CSR0_TXPKTRDY);
}
/*-------------------------------------------------------------------------*/
DBG(1, "HNP: Disabling HR\n");
hcd->self.is_b_host = 0;
musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
- reg = musb_readb(mbase, MGC_O_HDRC_POWER);
+ reg = musb_readb(mbase, MUSB_POWER);
reg |= MGC_M_POWER_SUSPENDM;
- musb_writeb(mbase, MGC_O_HDRC_POWER, reg);
+ musb_writeb(mbase, MUSB_POWER, reg);
/* REVISIT: Start SESSION_REQUEST here? */
break;
default:
}
power &= ~MGC_M_POWER_SUSPENDM;
- musb_writeb(mbase, MGC_O_HDRC_POWER,
+ musb_writeb(mbase, MUSB_POWER,
power | MGC_M_POWER_RESUME);
musb->port1_status |=
* - ... to A_WAIT_BCON.
* a_wait_vrise_tmout triggers VBUS_ERROR transitions
*/
- musb_writeb(mbase, MGC_O_HDRC_DEVCTL, MGC_M_DEVCTL_SESSION);
+ musb_writeb(mbase, MUSB_DEVCTL, MGC_M_DEVCTL_SESSION);
musb->ep0_stage = MGC_END0_START;
musb->xceiv.state = OTG_STATE_A_IDLE;
MUSB_HST_MODE(musb);
musb->vbuserr_retry--;
ignore = 1;
devctl |= MGC_M_DEVCTL_SESSION;
- musb_writeb(mbase, MGC_O_HDRC_DEVCTL, devctl);
+ musb_writeb(mbase, MUSB_DEVCTL, devctl);
} else {
musb->port1_status |=
(1 << USB_PORT_FEAT_OVER_CURRENT)
// REVISIT HNP; just force disconnect
}
musb->delay_port_power_off = FALSE;
- musb_writew(mbase, MGC_O_HDRC_INTRTXE, musb->wEndMask);
- musb_writew(mbase, MGC_O_HDRC_INTRRXE, musb->wEndMask & 0xfffe);
- musb_writeb(mbase, MGC_O_HDRC_INTRUSBE, 0xf7);
+ musb_writew(mbase, MUSB_INTRTXE, musb->wEndMask);
+ musb_writew(mbase, MUSB_INTRRXE, musb->wEndMask & 0xfffe);
+ musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
#endif
musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
|USB_PORT_STAT_HIGH_SPEED
DBG(1, "BABBLE devctl: %02x\n", devctl);
else {
ERR("Stopping host session because of babble\n");
- musb_writeb(mbase, MGC_O_HDRC_DEVCTL, 0);
+ musb_writeb(mbase, MUSB_DEVCTL, 0);
}
} else {
DBG(1, "BUS RESET\n");
handled = IRQ_HANDLED;
/* start any periodic Tx transfers waiting for current frame */
- wFrame = musb_readw(mbase, MGC_O_HDRC_FRAME);
+ wFrame = musb_readw(mbase, MUSB_FRAME);
ep = musb->endpoints;
for (epnum = 1; (epnum < musb->nr_endpoints)
&& (musb->wEndMask >= (1 << epnum));
void musb_start(struct musb *musb)
{
void __iomem *regs = musb->mregs;
- u8 devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
+ u8 devctl = musb_readb(regs, MUSB_DEVCTL);
DBG(2, "<== devctl %02x\n", devctl);
/* Set INT enable registers, enable interrupts */
- musb_writew(regs, MGC_O_HDRC_INTRTXE, musb->wEndMask);
- musb_writew(regs, MGC_O_HDRC_INTRRXE, musb->wEndMask & 0xfffe);
- musb_writeb(regs, MGC_O_HDRC_INTRUSBE, 0xf7);
+ musb_writew(regs, MUSB_INTRTXE, musb->wEndMask);
+ musb_writew(regs, MUSB_INTRRXE, musb->wEndMask & 0xfffe);
+ musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
- musb_writeb(regs, MGC_O_HDRC_TESTMODE, 0);
+ musb_writeb(regs, MUSB_TESTMODE, 0);
/* put into basic highspeed mode and start session */
- musb_writeb(regs, MGC_O_HDRC_POWER, MGC_M_POWER_ISOUPDATE
+ musb_writeb(regs, MUSB_POWER, MGC_M_POWER_ISOUPDATE
| MGC_M_POWER_SOFTCONN
| MGC_M_POWER_HSENAB
/* ENSUSPEND wedges tusb */
);
musb->is_active = 0;
- devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(regs, MUSB_DEVCTL);
devctl &= ~MGC_M_DEVCTL_SESSION;
if (is_otg_enabled(musb)) {
musb->is_active = 1;
}
musb_platform_enable(musb);
- musb_writeb(regs, MGC_O_HDRC_DEVCTL, devctl);
+ musb_writeb(regs, MUSB_DEVCTL, devctl);
}
u16 temp;
/* disable interrupts */
- musb_writeb(mbase, MGC_O_HDRC_INTRUSBE, 0);
- musb_writew(mbase, MGC_O_HDRC_INTRTXE, 0);
- musb_writew(mbase, MGC_O_HDRC_INTRRXE, 0);
+ musb_writeb(mbase, MUSB_INTRUSBE, 0);
+ musb_writew(mbase, MUSB_INTRTXE, 0);
+ musb_writew(mbase, MUSB_INTRRXE, 0);
/* off */
- musb_writeb(mbase, MGC_O_HDRC_DEVCTL, 0);
+ musb_writeb(mbase, MUSB_DEVCTL, 0);
/* flush pending interrupts */
- temp = musb_readb(mbase, MGC_O_HDRC_INTRUSB);
- temp = musb_readw(mbase, MGC_O_HDRC_INTRTX);
- temp = musb_readw(mbase, MGC_O_HDRC_INTRRX);
+ temp = musb_readb(mbase, MUSB_INTRUSB);
+ temp = musb_readw(mbase, MUSB_INTRTX);
+ temp = musb_readw(mbase, MUSB_INTRRX);
}
}
/* configure the FIFO */
- musb_writeb(mbase, MGC_O_HDRC_INDEX, hw_ep->epnum);
+ musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
#ifdef CONFIG_USB_MUSB_HDRC_HCD
/* EP0 reserved endpoint for control, bidirectional;
#endif
switch (cfg->style) {
case FIFO_TX:
- musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
- musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
+ musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
+ musb_writew(mbase, MUSB_TXFIFOADD, c_off);
hw_ep->tx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
hw_ep->max_packet_sz_tx = maxpacket;
break;
case FIFO_RX:
- musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
- musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
+ musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
+ musb_writew(mbase, MUSB_RXFIFOADD, c_off);
hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
hw_ep->max_packet_sz_rx = maxpacket;
break;
case FIFO_RXTX:
- musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
- musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
+ musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
+ musb_writew(mbase, MUSB_TXFIFOADD, c_off);
hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
hw_ep->max_packet_sz_rx = maxpacket;
- musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
- musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
+ musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
+ musb_writew(mbase, MUSB_RXFIFOADD, c_off);
hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
hw_ep->max_packet_sz_tx = maxpacket;
hw_ep = musb->endpoints + epnum;
/* read from core using indexed model */
- reg = musb_readb(hw_ep->regs, 0x10 + MGC_O_HDRC_FIFOSIZE);
+ reg = musb_readb(hw_ep->regs, 0x10 + MUSB_FIFOSIZE);
if (!reg) {
/* 0's returned when no more endpoints */
break;
/* log core options (read using indexed model) */
musb_ep_select(mbase, 0);
- reg = musb_readb(mbase, 0x10 + MGC_O_HDRC_CONFIGDATA);
+ reg = musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
strcpy(aInfo, (reg & MGC_M_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
}
/* log release info */
- wRelease = musb_readw(mbase, MGC_O_HDRC_HWVERS);
+ wRelease = musb_readw(mbase, MUSB_HWVERS);
wRelMajor = (wRelease >> 10) & 0x1f;
wRelMinor = wRelease & 0x3ff;
snprintf(aRevision, 32, "%d.%d%s", wRelMajor,
spin_lock_irqsave(&musb->lock, flags);
- musb->int_usb = musb_readb(musb->mregs, MGC_O_HDRC_INTRUSB);
- musb->int_tx = musb_readw(musb->mregs, MGC_O_HDRC_INTRTX);
- musb->int_rx = musb_readw(musb->mregs, MGC_O_HDRC_INTRRX);
+ musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
+ musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
+ musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
if (musb->int_usb || musb->int_tx || musb->int_rx)
retval = musb_interrupt(musb);
int ep_num;
u32 reg;
- devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
- power = musb_readb(musb->mregs, MGC_O_HDRC_POWER);
+ devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+ power = musb_readb(musb->mregs, MUSB_POWER);
DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
(devctl & MGC_M_DEVCTL_HM) ? "host" : "peripheral",
void musb_dma_completion(struct musb *musb, u8 epnum, u8 bTransmit)
{
- u8 devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
+ u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
/* called with controller lock already held */
* VBUS high for a long time after power has been removed, can
* cause temporary false indications of a connection.
*/
- vbus = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
+ vbus = musb_readb(musb->mregs, MUSB_DEVCTL);
if (vbus & 0x10) {
/* REVISIT retest on real OTG hardware */
switch (musb->board_mode) {
dma_controller_destroy(c);
}
- musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, 0);
+ musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
musb_platform_exit(musb);
- musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, 0);
+ musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
if (musb->clock) {
clk_disable(musb->clock);
DBG(1, "%s mode, status %d, devctl %02x %c\n",
"HOST", status,
- musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL),
- (musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL)
+ musb_readb(musb->mregs, MUSB_DEVCTL),
+ (musb_readb(musb->mregs, MUSB_DEVCTL)
& MGC_M_DEVCTL_BDEVICE
? 'B' : 'A'));
DBG(1, "%s mode, status %d, dev%02x\n",
is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
status,
- musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL));
+ musb_readb(musb->mregs, MUSB_DEVCTL));
}
prcm = musb_readl(base, TUSB_PRCM_MNGMT);
conf = musb_readl(base, TUSB_DEV_CONF);
- devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
if (is_on) {
if (musb->set_clock)
musb_writel(base, TUSB_PRCM_MNGMT, prcm);
musb_writel(base, TUSB_DEV_OTG_TIMER, timer);
musb_writel(base, TUSB_DEV_CONF, conf);
- musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, devctl);
+ musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
otg_state_string(musb),
- musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL),
+ musb_readb(musb->mregs, MUSB_DEVCTL),
musb_readl(base, TUSB_DEV_OTG_STAT),
conf, prcm);
}
case OTG_STATE_A_IDLE:
DBG(2, "Got SRP, turning on VBUS\n");
devctl = musb_readb(musb->mregs,
- MGC_O_HDRC_DEVCTL);
+ MUSB_DEVCTL);
devctl |= MGC_M_DEVCTL_SESSION;
- musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL,
+ musb_writeb(musb->mregs, MUSB_DEVCTL,
devctl);
musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
/* VBUS has probably been valid for a while now,
* but may well have bounced out of range a bit
*/
- devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
+ devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
if ((devctl & MGC_M_DEVCTL_VBUS)
!= MGC_M_DEVCTL_VBUS) {
if (chdat->tx) {
DBG(2, "terminating short tx packet\n");
musb_ep_select(musb_base, chdat->epnum);
- csr = musb_readw(hw_ep->regs, MGC_O_HDRC_TXCSR);
+ csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
csr |= MGC_M_TXCSR_MODE | MGC_M_TXCSR_TXPKTRDY
| MGC_M_TXCSR_P_WZC_BITS;
- musb_writew(hw_ep->regs, MGC_O_HDRC_TXCSR, csr);
+ musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
}
}
*/
if (chdat->tx) {
musb_ep_select(musb_base, chdat->epnum);
- csr = musb_readw(hw_ep->regs, MGC_O_HDRC_TXCSR);
+ csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
csr |= (MGC_M_TXCSR_AUTOSET | MGC_M_TXCSR_DMAENAB
| MGC_M_TXCSR_DMAMODE | MGC_M_TXCSR_MODE);
csr &= ~MGC_M_TXCSR_P_UNDERRUN;
- musb_writew(hw_ep->regs, MGC_O_HDRC_TXCSR, csr);
+ musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
} else {
musb_ep_select(musb_base, chdat->epnum);
- csr = musb_readw(hw_ep->regs, MGC_O_HDRC_RXCSR);
+ csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
csr |= MGC_M_RXCSR_DMAENAB;
csr &= ~(MGC_M_RXCSR_AUTOCLEAR | MGC_M_RXCSR_DMAMODE);
- musb_writew(hw_ep->regs, MGC_O_HDRC_RXCSR,
+ musb_writew(hw_ep->regs, MUSB_RXCSR,
csr | MGC_M_RXCSR_P_WZC_BITS);
}
* MGC_M_POWER_ENSUSPEND. PHY may need a clock (sigh) to detect
* SE0 changing to connect (J) or wakeup (K) states.
*/
- power = musb_readb(mbase, MGC_O_HDRC_POWER);
+ power = musb_readb(mbase, MUSB_POWER);
if (bSuspend) {
int retries = 10000;
power &= ~MGC_M_POWER_RESUME;
power |= MGC_M_POWER_SUSPENDM;
- musb_writeb(mbase, MGC_O_HDRC_POWER, power);
+ musb_writeb(mbase, MUSB_POWER, power);
/* Needed for OPT A tests */
- power = musb_readb(mbase, MGC_O_HDRC_POWER);
+ power = musb_readb(mbase, MUSB_POWER);
while (power & MGC_M_POWER_SUSPENDM) {
- power = musb_readb(mbase, MGC_O_HDRC_POWER);
+ power = musb_readb(mbase, MUSB_POWER);
if (retries-- < 1)
break;
}
} else if (power & MGC_M_POWER_SUSPENDM) {
power &= ~MGC_M_POWER_SUSPENDM;
power |= MGC_M_POWER_RESUME;
- musb_writeb(mbase, MGC_O_HDRC_POWER, power);
+ musb_writeb(mbase, MUSB_POWER, power);
DBG(3, "Root port resuming, power %02x\n", power);
#ifdef CONFIG_USB_MUSB_OTG
/* REVISIT this looks wrong for HNP */
- u8 devctl = musb_readb(mbase, MGC_O_HDRC_DEVCTL);
+ u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
if (musb->delay_port_power_off || !(devctl & MGC_M_DEVCTL_HM)) {
return;
/* NOTE: caller guarantees it will turn off the reset when
* the appropriate amount of time has passed
*/
- power = musb_readb(mbase, MGC_O_HDRC_POWER);
+ power = musb_readb(mbase, MUSB_POWER);
if (bReset) {
/*
if (power & MGC_M_POWER_RESUME) {
while (time_before(jiffies, musb->rh_timer))
msleep(1);
- musb_writeb(mbase, MGC_O_HDRC_POWER,
+ musb_writeb(mbase, MUSB_POWER,
power & ~MGC_M_POWER_RESUME);
msleep(1);
}
musb->ignore_disconnect = TRUE;
power &= 0xf0;
- musb_writeb(mbase, MGC_O_HDRC_POWER,
+ musb_writeb(mbase, MUSB_POWER,
power | MGC_M_POWER_RESET);
musb->port1_status |= USB_PORT_STAT_RESET;
musb->rh_timer = jiffies + msecs_to_jiffies(50);
} else {
DBG(4, "root port reset stopped\n");
- musb_writeb(mbase, MGC_O_HDRC_POWER,
+ musb_writeb(mbase, MUSB_POWER,
power & ~MGC_M_POWER_RESET);
musb->ignore_disconnect = FALSE;
- power = musb_readb(mbase, MGC_O_HDRC_POWER);
+ power = musb_readb(mbase, MUSB_POWER);
if (power & MGC_M_POWER_HSMODE) {
DBG(4, "high-speed device connected\n");
musb->port1_status |= USB_PORT_STAT_HIGH_SPEED;
&& time_after(jiffies, musb->rh_timer)) {
u8 power;
- power = musb_readb(musb->mregs, MGC_O_HDRC_POWER);
+ power = musb_readb(musb->mregs, MUSB_POWER);
power &= ~MGC_M_POWER_RESUME;
DBG(4, "root port resume stopped, power %02x\n",
power);
- musb_writeb(musb->mregs, MGC_O_HDRC_POWER, power);
+ musb_writeb(musb->mregs, MUSB_POWER, power);
/* ISSUE: DaVinci (RTL 1.300) disconnects after
* resume of high speed peripherals (but not full
temp = MGC_M_TEST_FORCE_HOST
| MGC_M_TEST_FORCE_HS;
- musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, MGC_M_DEVCTL_SESSION);
+ musb_writeb(musb->mregs, MUSB_DEVCTL, MGC_M_DEVCTL_SESSION);
break;
case 6:
pr_debug("TEST_FIFO_ACCESS\n");
default:
goto error;
}
- musb_writeb(musb->mregs, MGC_O_HDRC_TESTMODE, temp);
+ musb_writeb(musb->mregs, MUSB_TESTMODE, temp);
break;
default:
goto error;
projects / linux-2.6-omap-h63xx.git / commitdiff