OMAP3 pwrdm: add CORE SAR handling (for USBTLL module)

34xx TRM Delta G->H notes that the CORE powerdomain has a hardware
save-and-restore (SAR) control bit for the USBTLL module, similar to
the USBHOST powerdomain SAR bit.  Split the existing core_34xx struct
powerdomain into two structs, one for ES1 and one for ES2, and add the
PWRDM_HAS_HDWR_SAR flag to the ES2 powerdomain.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h
index 5ad9cb0c17558a226f1ce35f642157324fd11dd7..315281148c01ab07cbb3b072c025e471debb75fa 100644 (file)
--- a/arch/arm/mach-omap2/powerdomains.h
+++ b/arch/arm/mach-omap2/powerdomains.h
@@ -171,7 +171,8 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
        &iva2_pwrdm,
        &mpu_34xx_pwrdm,
        &neon_pwrdm,
-       &core_34xx_pwrdm,
+       &core_34xx_es1_pwrdm,
+       &core_34xx_es2_pwrdm,
        &cam_pwrdm,
        &dss_pwrdm,
        &per_pwrdm,

diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index 88f85eaa3b7fb2eef14dee484787fef8644025f5..0c07bf75715b380b4aea4756d0e2b0f484d66d86 100644 (file)
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -200,12 +200,31 @@ static struct powerdomain mpu_34xx_pwrdm = {
 };
 
 /* No wkdeps or sleepdeps for 34xx core apparently */
-static struct powerdomain core_34xx_pwrdm = {
+static struct powerdomain core_34xx_es1_pwrdm = {
        .name             = "core_pwrdm",
        .prcm_offs        = CORE_MOD,
-       .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+       .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
+       .pwrsts           = PWRSTS_OFF_RET_ON,
+       .dep_bit          = OMAP3430_EN_CORE_SHIFT,
+       .banks            = 2,
+       .pwrsts_mem_ret   = {
+               [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
+               [1] = PWRSTS_OFF_RET,    /* MEM2RETSTATE */
+       },
+       .pwrsts_mem_on    = {
+               [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
+               [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
+       },
+};
+
+/* No wkdeps or sleepdeps for 34xx core apparently */
+static struct powerdomain core_34xx_es2_pwrdm = {
+       .name             = "core_pwrdm",
+       .prcm_offs        = CORE_MOD,
+       .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
        .pwrsts           = PWRSTS_OFF_RET_ON,
        .dep_bit          = OMAP3430_EN_CORE_SHIFT,
+       .flags            = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
        .banks            = 2,
        .pwrsts_mem_ret   = {
                [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */