#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
+#include "prm.h"
+#include "cm.h"
+
static void omap2_sys_clk_recalc(struct clk * clk);
static void omap2_clksel_recalc(struct clk * clk);
static void omap2_followparent_recalc(struct clk * clk);
.rate = 96000000,
.flags = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = 0x2,
.recalc = &omap2_propagate_rate,
};
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = 0x6,
.recalc = &omap2_propagate_rate,
};
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
.src_offset = 5,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = PARENT_CONTROLS_CLOCK,
.recalc = &omap2_propagate_rate,
};
.rate = 96000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = PARENT_CONTROLS_CLOCK,
.recalc = &omap2_propagate_rate,
};
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
.src_offset = 3,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = PARENT_CONTROLS_CLOCK,
.recalc = &omap2_propagate_rate,
};
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
.recalc = &omap2_propagate_rate,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = PARENT_CONTROLS_CLOCK,
};
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
.src_offset = 0,
- .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
+ .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
.enable_bit = 7,
.rate_offset = 3,
.recalc = &omap2_clksel_recalc,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
.src_offset = 8,
- .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
+ .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
.enable_bit = 15,
.rate_offset = 11,
.recalc = &omap2_clksel_recalc,
.name = "emul_ck",
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&PRCM_CLKEMUL_CTRL,
+ .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
.enable_bit = 0,
.recalc = &omap2_propagate_rate,
DELAYED_APP | RATE_PROPAGATES |
CONFIG_PARTICIPANT,
.rate_offset = 0,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
.enable_bit = 0,
.recalc = &omap2_clksel_recalc,
};
.flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
.rate_offset = 0,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
.enable_bit = 0,
.recalc = &omap2_clksel_recalc,
};
.flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
DELAYED_APP | CONFIG_PARTICIPANT,
.rate_offset = 5,
- .enable_reg = (void __iomem *)&CM_ICLKEN_DSP,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
.enable_bit = 1, /* for ipi */
.recalc = &omap2_clksel_recalc,
};
.flags = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
.rate_offset = 8,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
.enable_bit = 10,
.recalc = &omap2_clksel_recalc,
};
.name = "iva1_mpu_int_ifck",
.parent = &iva1_ifck,
.flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
.enable_bit = 8,
.recalc = &omap2_clksel_recalc,
};
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
CONFIG_PARTICIPANT,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = 0,
.rate_offset = 25,
.recalc = &omap2_clksel_recalc,
.parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, /* bit 1 */
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), /* bit 1 */
.enable_bit = 1,
.rate_offset = 20,
.recalc = &omap2_clksel_recalc,
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_GFX_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
.enable_bit = 2,
.rate_offset = 0,
.recalc = &omap2_clksel_recalc,
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_GFX_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
.enable_bit = 1,
.rate_offset = 0,
.recalc = &omap2_clksel_recalc,
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL,
- .enable_reg = (void __iomem *)&CM_ICLKEN_GFX, /* bit 0 */
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), /* bit 0 */
.enable_bit = 0,
.recalc = &omap2_followparent_recalc,
};
.flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
DELAYED_APP | CONFIG_PARTICIPANT,
.rate_offset = 0,
- .enable_reg = (void __iomem *)&CM_ICLKEN_MDM,
+ .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
.enable_bit = 0,
.recalc = &omap2_clksel_recalc,
};
.rate = 26000000,
.parent = &osc_ck,
.flags = CLOCK_IN_OMAP243X | RATE_FIXED,
- .enable_reg = (void __iomem *)&CM_FCLKEN_MDM,
+ .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
.enable_bit = 1,
.recalc = &omap2_followparent_recalc,
};
.name = "ssi_l4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, /* bit 1 */
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), /* bit 1 */
.enable_bit = 1,
.recalc = &omap2_followparent_recalc,
};
.name = "dss_ick",
.parent = &l4_ck, /* really both l3 and l4 */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 0,
.recalc = &omap2_followparent_recalc,
};
.parent = &core_ck, /* Core or sys */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 0,
.rate_offset = 8,
.src_offset = 8,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 1,
.src_offset = 13,
.recalc = &omap2_followparent_recalc,
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 2,
.recalc = &omap2_propagate_rate,
};
.name = "gpt1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, /* Bit0 */
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), /* Bit0 */
.enable_bit = 0,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_WKUP_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, /* Bit0 */
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN), /* Bit0 */
.enable_bit = 0,
.src_offset = 0,
.recalc = &omap2_followparent_recalc,
.name = "gpt2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* Bit4 */
.enable_bit = 4,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 4,
.src_offset = 2,
.recalc = &omap2_followparent_recalc,
.name = "gpt3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit5 */
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* Bit5 */
.enable_bit = 5,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 5,
.src_offset = 4,
.recalc = &omap2_followparent_recalc,
.name = "gpt4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit6 */
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* Bit6 */
.enable_bit = 6,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 6,
.src_offset = 6,
.recalc = &omap2_followparent_recalc,
.name = "gpt5_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit7 */
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* Bit7 */
.enable_bit = 7,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 7,
.src_offset = 8,
.recalc = &omap2_followparent_recalc,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_bit = 8,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit8 */
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* bit8 */
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 8,
.src_offset = 10,
.recalc = &omap2_followparent_recalc,
.name = "gpt7_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit9 */
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* bit9 */
.enable_bit = 9,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 9,
.src_offset = 12,
.recalc = &omap2_followparent_recalc,
.name = "gpt8_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit10 */
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* bit10 */
.enable_bit = 10,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 10,
.src_offset = 14,
.recalc = &omap2_followparent_recalc,
.name = "gpt9_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 11,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 11,
.src_offset = 16,
.recalc = &omap2_followparent_recalc,
.name = "gpt10_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 12,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 12,
.src_offset = 18,
.recalc = &omap2_followparent_recalc,
.name = "gpt11_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 13,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 13,
.src_offset = 20,
.recalc = &omap2_followparent_recalc,
.name = "gpt12_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit14 */
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* bit14 */
.enable_bit = 14,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 14,
.src_offset = 22,
.recalc = &omap2_followparent_recalc,
.name = "mcbsp1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit16 */
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* bit16 */
.enable_bit = 15,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp1_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 15,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 16,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp2_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 16,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp3_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = 4,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp4_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = 4,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp5_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = 5,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp5_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = 5,
.recalc = &omap2_followparent_recalc,
};
.id = 1,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 17,
.recalc = &omap2_followparent_recalc,
};
.id = 1,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 17,
.recalc = &omap2_followparent_recalc,
};
.id = 2,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 18,
.recalc = &omap2_followparent_recalc,
};
.id = 2,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 18,
.recalc = &omap2_followparent_recalc,
};
.id = 3,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = 9,
.recalc = &omap2_followparent_recalc,
};
.id = 3,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = 9,
.recalc = &omap2_followparent_recalc,
};
.name = "uart1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 21,
.recalc = &omap2_followparent_recalc,
};
.name = "uart1_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 21,
.recalc = &omap2_followparent_recalc,
};
.name = "uart2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 22,
.recalc = &omap2_followparent_recalc,
};
.name = "uart2_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 22,
.recalc = &omap2_followparent_recalc,
};
.name = "uart3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
.name = "uart3_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
.name = "gpios_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
.name = "gpios_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
.name = "mpu_wdt_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
.name = "mpu_wdt_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
.name = "sync_32k_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = 1,
.recalc = &omap2_followparent_recalc,
};
.name = "wdt1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = 4,
.recalc = &omap2_followparent_recalc,
};
.name = "omapctrl_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = 5,
.recalc = &omap2_followparent_recalc,
};
.name = "icr_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = 6,
.recalc = &omap2_followparent_recalc,
};
.name = "cam_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 31,
.recalc = &omap2_followparent_recalc,
};
.name = "cam_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 31,
.recalc = &omap2_followparent_recalc,
};
.name = "mailboxes_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 30,
.recalc = &omap2_followparent_recalc,
};
.name = "wdt4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 29,
.recalc = &omap2_followparent_recalc,
};
.name = "wdt4_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 29,
.recalc = &omap2_followparent_recalc,
};
.name = "wdt3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 28,
.recalc = &omap2_followparent_recalc,
};
.name = "wdt3_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 28,
.recalc = &omap2_followparent_recalc,
};
.name = "mspro_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 27,
.recalc = &omap2_followparent_recalc,
};
.name = "mspro_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 27,
.recalc = &omap2_followparent_recalc,
};
.name = "mmc_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 26,
.recalc = &omap2_followparent_recalc,
};
.name = "mmc_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 26,
.recalc = &omap2_followparent_recalc,
};
.name = "fac_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 25,
.recalc = &omap2_followparent_recalc,
};
.name = "fac_fck",
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 25,
.recalc = &omap2_followparent_recalc,
};
.name = "eac_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 24,
.recalc = &omap2_followparent_recalc,
};
.name = "eac_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 24,
.recalc = &omap2_followparent_recalc,
};
.name = "hdq_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 23,
.recalc = &omap2_followparent_recalc,
};
.name = "hdq_fck",
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 23,
.recalc = &omap2_followparent_recalc,
};
.id = 2,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 20,
.recalc = &omap2_followparent_recalc,
};
.id = 2,
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 20,
.recalc = &omap2_followparent_recalc,
};
.id = 2,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = 20,
.recalc = &omap2_followparent_recalc,
};
.id = 1,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 19,
.recalc = &omap2_followparent_recalc,
};
.id = 1,
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 19,
.recalc = &omap2_followparent_recalc,
};
.id = 1,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = 19,
.recalc = &omap2_followparent_recalc,
};
.name = "vlynq_ick",
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
.name = "vlynq_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = 3,
.src_offset = 15,
.recalc = &omap2_followparent_recalc,
.name = "sdrc_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN3_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
.name = "des_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
.enable_bit = 0,
.recalc = &omap2_followparent_recalc,
};
.name = "sha_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
.enable_bit = 1,
.recalc = &omap2_followparent_recalc,
};
.name = "rng_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
.enable_bit = 2,
.recalc = &omap2_followparent_recalc,
};
.name = "aes_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
.enable_bit = 3,
.recalc = &omap2_followparent_recalc,
};
.name = "pka_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
.enable_bit = 4,
.recalc = &omap2_followparent_recalc,
};
.name = "usb_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = 0,
.recalc = &omap2_followparent_recalc,
};
.name = "usbhs_ick",
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = 6,
.recalc = &omap2_followparent_recalc,
};
.name = "mmchs1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = 7,
.recalc = &omap2_followparent_recalc,
};
.name = "mmchs1_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = 7,
.recalc = &omap2_followparent_recalc,
};
.name = "mmchs2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = 8,
.recalc = &omap2_followparent_recalc,
};
.name = "mmchs2_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = 8,
.recalc = &omap2_followparent_recalc,
};
.name = "gpio5_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = 10,
.recalc = &omap2_followparent_recalc,
};
.name = "gpio5_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = 10,
.recalc = &omap2_followparent_recalc,
};
.name = "mdm_intc_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = 11,
.recalc = &omap2_followparent_recalc,
};
.name = "mmchsdb1_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = 16,
.recalc = &omap2_followparent_recalc,
};
.name = "mmchsdb2_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = 17,
.recalc = &omap2_followparent_recalc,
};