PRM/CM: Convert existing code to use PRM/CM RMW functions

Convert existing code that reads, modifies, and writes back CM/PRM
register values to use the rmw functions introduced in the previous
patch.  This code should eventually disappear once clockdomain handling
is integrated into the 24xx clock framework.

Also restructure arch/arm/mach-omap2/prcm.c slightly while we
are here.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 5661cb829e04f3d4b6125e709af0edfbc3823c37..250a33f34334c857dafb125678fe9a8a876f460f 100644 (file)
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -577,7 +577,7 @@ u32 omap2_clksel_get_divisor(struct clk *clk)
 
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 {
-       u32 field_mask, field_val, reg_val, validrate, new_div = 0;
+       u32 field_mask, field_val, validrate, new_div = 0;
        void __iomem *div_addr;
 
        validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
@@ -592,10 +592,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
        if (field_val == ~0)
                return -EINVAL;
 
-       reg_val = cm_read_reg(div_addr);
-       reg_val &= ~field_mask;
-       reg_val |= (field_val << __ffs(field_mask));
-       cm_write_reg(reg_val, div_addr);
+       cm_rmw_reg_bits(field_mask, field_val << __ffs(field_mask), div_addr);
+
        wmb();
 
        clk->rate = clk->parent->rate / new_div;

diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index c6391b065294ad4be6b7e9e7e6fcf6eba4aacc3c..5ea48ff8d4ec387220438d3efc62656ff520ce90 100644 (file)
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -77,24 +77,17 @@ static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
 
 static int omap2_enable_osc_ck(struct clk *clk)
 {
-       u32 pcc;
 
-       pcc = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
-
-       prm_write_reg(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
-                     OMAP24XX_PRCM_CLKSRC_CTRL);
+       prm_rmw_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, ~OMAP_AUTOEXTCLKMODE_MASK,
+                        OMAP24XX_PRCM_CLKSRC_CTRL);
 
        return 0;
 }
 
 static void omap2_disable_osc_ck(struct clk *clk)
 {
-       u32 pcc;
-
-       pcc = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
-
-       prm_write_reg(pcc | OMAP_AUTOEXTCLKMODE_MASK,
-                     OMAP24XX_PRCM_CLKSRC_CTRL);
+       prm_rmw_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP_AUTOEXTCLKMODE_MASK,
+                        OMAP24XX_PRCM_CLKSRC_CTRL);
 }
 
 /* Enable an APLL if off */

diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 5ba42da455d85888662e8cffb4a0f01c96df41a6..996888526a5e0e819ab9e266f69170c4e9317e1f 100644 (file)
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -162,7 +162,6 @@ static void pm_init_serial_console(void)
 {
        const struct omap_serial_console_config *conf;
        char name[16];
-       u32 l;
 
        conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
                               struct omap_serial_console_config);
@@ -185,19 +184,13 @@ static void pm_init_serial_console(void)
        }
        switch (serial_console_uart) {
        case 1:
-               l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
-               l |= OMAP24XX_ST_UART1;
-               prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
+               prm_set_mod_reg_bits(OMAP24XX_ST_UART1, CORE_MOD, PM_WKEN1)
                break;
        case 2:
-               l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
-               l |= OMAP24XX_ST_UART2;
-               prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
+               prm_set_mod_reg_bits(OMAP24XX_ST_UART2, CORE_MOD, PM_WKEN1)
                break;
        case 3:
-               l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKEN2);
-               l |= OMAP24XX_ST_UART3;
-               prm_write_mod_reg(l, CORE_MOD, OMAP24XX_PM_WKEN2);
+               prm_set_mod_reg_bits(OMAP24XX_ST_UART3, CORE_MOD, PM_WKEN2)
                break;
        }
 }
@@ -445,10 +438,8 @@ no_sleep:
        prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
        prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 
-       /* wakeup domain events */
-       l = prm_read_mod_reg(WKUP_MOD, PM_WKST);
-       l &= 0x5;  /* bit 1: GPT1, bit5 GPIO */
-       prm_write_mod_reg(l, WKUP_MOD, PM_WKST);
+       /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
+       prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 
        /* MPU domain wake events */
        l = prm_read_reg(OMAP24XX_PRCM_IRQSTATUS_MPU);

diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index e0035987eb4e8bd52f1f3e0926771077511f9650..c1b4cc5505d48a221f8963cae38d2b0298052dba 100644 (file)
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -25,6 +25,7 @@ extern void omap2_clk_prepare_for_reboot(void);
 
 u32 omap_prcm_get_reset_sources(void)
 {
+       /* XXX This presumably needs modification for 34XX */
        return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
 }
 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
@@ -32,15 +33,16 @@ EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 /* Resets clock rates and reboots the system. Only called from system.h */
 void omap_prcm_arch_reset(char mode)
 {
-       u32 wkup;
+       s16 prcm_offs;
        omap2_clk_prepare_for_reboot();
 
        if (cpu_is_omap24xx()) {
-               wkup = prm_read_mod_reg(WKUP_MOD, RM_RSTCTRL) | OMAP_RST_DPLL3;
-               prm_write_mod_reg(wkup, WKUP_MOD, RM_RSTCTRL);
+               prcm_offs = WKUP_MOD;
        } else if (cpu_is_omap34xx()) {
-               wkup = prm_read_mod_reg(OMAP3430_GR_MOD, RM_RSTCTRL)
-                                                       | OMAP_RST_DPLL3;
-               prm_write_mod_reg(wkup, OMAP3430_GR_MOD, RM_RSTCTRL);
+               prcm_offs = OMAP3430_GR_MOD;
+       } else {
+               WARN_ON(1);
        }
+
+       prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
 }

diff --git a/drivers/dsp/dspgateway/dsp_core.c b/drivers/dsp/dspgateway/dsp_core.c
index 05274bebbd1075c50997ad910ed9bafd3422e08e..6873ca511c25a714f7915171abd32da6731ff3ca 100644 (file)
--- a/drivers/dsp/dspgateway/dsp_core.c
+++ b/drivers/dsp/dspgateway/dsp_core.c
@@ -460,19 +460,15 @@ static inline void dsp_clk_disable(void) {}
 #elif defined(CONFIG_ARCH_OMAP2)
 static inline void dsp_clk_enable(void)
 {
-       u32 r;
-
        /*XXX should be handled in mach-omap[1,2] XXX*/
        prm_write_mod_reg(OMAP24XX_FORCESTATE | (1 << OMAP_POWERSTATE_SHIFT),
                          OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 
-       r = cm_read_mod_reg(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
-       r |= OMAP2420_AUTO_DSP_IPI;
-       cm_write_mod_reg(r, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
+       cm_set_mod_reg_bits(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD,
+                           CM_AUTOIDLE);
 
-       r = cm_read_mod_reg(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
-       r |= OMAP24XX_AUTOSTATE_DSP;
-       cm_write_mod_reg(r, OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
+       cm_set_mod_reg_bits(OMAP24XX_AUTOSTATE_DSP, OMAP24XX_DSP_MOD,
+                           CM_CLKSTCTRL);
 
        clk_enable(dsp_fck_handle);
        clk_enable(dsp_ick_handle);