drm/i915 more registers for S3 (DSPCLK_GATE_D, CACHE_MODE_0, MI_ARB_STATE)

Failing to preserve the MI_ARB_STATE register was causing FIFO underruns on
the VGA output on my HP 2510p after resume.

Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c
index 248e7b1c46a568aa9f3af977e5b8320fffd2f725..5025f5b02412a9fe885053fea44d845d78c602d3 100644 (file)
--- a/drivers/char/drm/i915_drv.c
+++ b/drivers/char/drm/i915_drv.c
@@ -342,6 +342,15 @@ static int i915_suspend(struct drm_device *dev)
        dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
        dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
 
+       /* Clock gating state */
+       dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
+
+       /* Cache mode state */
+       dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
+
+       /* Memory Arbitration state */
+       dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
+
        /* Scratch space */
        for (i = 0; i < 16; i++) {
                dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
@@ -489,6 +498,15 @@ static int i915_resume(struct drm_device *dev)
        I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
        udelay(150);
 
+       /* Clock gating state */
+       I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
+
+       /* Cache mode state */
+       I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
+
+       /* Memory arbitration state */
+       I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
+
        for (i = 0; i < 16; i++) {
                I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
                I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);

diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h
index 360f6600427b21919f93b9a39b4129ec01eb6b56..c10d128e34dbd08beb949eef706d3ab11cee3a71 100644 (file)
--- a/drivers/char/drm/i915_drv.h
+++ b/drivers/char/drm/i915_drv.h
@@ -187,6 +187,9 @@ typedef struct drm_i915_private {
        u32 saveIER;
        u32 saveIIR;
        u32 saveIMR;
+       u32 saveCACHE_MODE_0;
+       u32 saveDSPCLK_GATE_D;
+       u32 saveMI_ARB_STATE;
        u32 saveSWF0[16];
        u32 saveSWF1[16];
        u32 saveSWF2[3];
@@ -455,6 +458,10 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
  */
 #define DMA_FADD_S             0x20d4
 
+/* Memory Interface Arbitration State
+ */
+#define MI_ARB_STATE           0x20e4
+
 /* Cache mode 0 reg.
  *  - Manipulating render cache behaviour is central
  *    to the concept of zone rendering, tuning this reg can help avoid
@@ -465,6 +472,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
  * bit of interest either set or cleared.  EG: (BIT<<16) | BIT to set.
  */
 #define Cache_Mode_0           0x2120
+#define CACHE_MODE_0           0x2120
 #define CM0_MASK_SHIFT          16
 #define CM0_IZ_OPT_DISABLE      (1<<6)
 #define CM0_ZR_OPT_DISABLE      (1<<5)
@@ -660,6 +668,8 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 /** P1 value is 2 greater than this field */
 # define VGA0_PD_P1_MASK       (0x1f << 0)
 
+#define DSPCLK_GATE_D  0x6200
+
 /* I830 CRTC registers */
 #define HTOTAL_A       0x60000
 #define HBLANK_A       0x60004