]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
[ARM] mv78xx0: wire up ethernet error interrupt
authorLennert Buytenhek <buytenh@wantstofly.org>
Tue, 26 Aug 2008 14:04:05 +0000 (16:04 +0200)
committerNicolas Pitre <nico@cam.org>
Thu, 25 Sep 2008 20:26:44 +0000 (16:26 -0400)
Wire up the ethernet port's error interrupt so that the
mv643xx_eth driver can sleep for SMI event completion instead of
having to busy-wait for it.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
arch/arm/mach-mv78xx0/common.c
arch/arm/mach-mv78xx0/include/mach/entry-macro.S
arch/arm/mach-mv78xx0/include/mach/irqs.h
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
arch/arm/mach-mv78xx0/irq.c

index 953a26c469cb0b9cf0602ec038e75d81129b7405..d56a05e8356b0a88a994a11b2e3e9edf8ce7e8a9 100644 (file)
@@ -285,6 +285,11 @@ static struct resource mv78xx0_ge00_shared_resources[] = {
                .start  = GE00_PHYS_BASE + 0x2000,
                .end    = GE00_PHYS_BASE + 0x3fff,
                .flags  = IORESOURCE_MEM,
+       }, {
+               .name   = "ge err irq",
+               .start  = IRQ_MV78XX0_GE_ERR,
+               .end    = IRQ_MV78XX0_GE_ERR,
+               .flags  = IORESOURCE_IRQ,
        },
 };
 
@@ -294,7 +299,7 @@ static struct platform_device mv78xx0_ge00_shared = {
        .dev            = {
                .platform_data  = &mv78xx0_ge00_shared_data,
        },
-       .num_resources  = 1,
+       .num_resources  = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
        .resource       = mv78xx0_ge00_shared_resources,
 };
 
index ed4a46bcd3b0803b67bac56adffd782926f6d60f..fbfb2693ce6c71ff3a3f915f3f44e0ab2fbc399e 100644 (file)
        ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
        mov     \irqnr, #31
        ands    \irqstat, \irqstat, \tmp
+       bne     1001f
 
        @ if no low interrupts set, check high interrupts
-       ldreq   \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
-       ldreq   \tmp, [\base, #IRQ_MASK_HIGH_OFF]
-       moveq   \irqnr, #63
-       andeqs  \irqstat, \irqstat, \tmp
+       ldr     \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
+       ldr     \tmp, [\base, #IRQ_MASK_HIGH_OFF]
+       mov     \irqnr, #63
+       ands    \irqstat, \irqstat, \tmp
+       bne     1001f
+
+       @ if no high interrupts set, check error interrupts
+       ldr     \irqstat, [\base, #IRQ_CAUSE_ERR_OFF]
+       ldr     \tmp, [\base, #IRQ_MASK_ERR_OFF]
+       mov     \irqnr, #95
+       ands    \irqstat, \irqstat, \tmp
 
        @ find first active interrupt source
-       clzne   \irqstat, \irqstat
+1001:  clzne   \irqstat, \irqstat
        subne   \irqnr, \irqnr, \irqstat
        .endm
index 995d7fb8d06f60c252b77f13a8ccdff17f050885..bebc330281ec6173c056e0757dd2ce8f019bce27 100644 (file)
 #define IRQ_MV78XX0_DB_IN      60
 #define IRQ_MV78XX0_DB_OUT     61
 
+/*
+ * MV78xx0 Error Interrupt Controller
+ */
+#define IRQ_MV78XX0_GE_ERR     70
+
 /*
  * MV78XX0 General Purpose Pins
  */
-#define IRQ_MV78XX0_GPIO_START 64
+#define IRQ_MV78XX0_GPIO_START 96
 #define NR_GPIO_IRQS           GPIO_MAX
 
 #define NR_IRQS                        (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
index ad664178d6e1948176e5e58dac157edf6b044056..ee9c5593ee92bcfe957b8e11131ebf1cc1054f17 100644 (file)
 #define   BRIDGE_INT_TIMER1    0x0004
 #define   BRIDGE_INT_TIMER1_CLR        (~0x0004)
 #define  IRQ_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0200)
+#define   IRQ_CAUSE_ERR_OFF    0x0000
 #define   IRQ_CAUSE_LOW_OFF    0x0004
 #define   IRQ_CAUSE_HIGH_OFF   0x0008
+#define   IRQ_MASK_ERR_OFF     0x000c
 #define   IRQ_MASK_LOW_OFF     0x0010
 #define   IRQ_MASK_HIGH_OFF    0x0014
 #define  TIMER_VIRT_BASE       (BRIDGE_VIRT_BASE | 0x0300)
index 28248d37b999b944e3ef307d0c07200cb64a61a2..503e5d195ae548d9091486dda5b8b860d979dac1 100644 (file)
@@ -19,4 +19,5 @@ void __init mv78xx0_init_irq(void)
 {
        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+       orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
 }