atmel_spi throughput improvement

Don't insert (undesirable) delays between consecutive words (DLYBCT) or when
activating chipselects (DLYBS).

Removing the between-word delays improves the performance of bulk transfers
(such as mtd_dataflash, m25p80, mmc_spi) significantly.  In one test, the
improvement was a factor of more than eight!

(The large DLYBCT value came from the legacy at91 SPI driver, and it's not
clear why it used such a huge value.)

Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index ff10808183a36f4e9d642469e42653d50f13ca24..b09d33678dd8fc36c9edcc3c9e9773ba4c1f0d41 100644 (file)
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -490,9 +490,14 @@ static int atmel_spi_setup(struct spi_device *spi)
        if (!(spi->mode & SPI_CPHA))
                csr |= SPI_BIT(NCPHA);
 
-       /* TODO: DLYBS and DLYBCT */
-       csr |= SPI_BF(DLYBS, 10);
-       csr |= SPI_BF(DLYBCT, 10);
+       /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
+        *
+        * DLYBCT would add delays between words, slowing down transfers.
+        * It could potentially be useful to cope with DMA bottlenecks, but
+        * in those cases it's probably best to just use a lower bitrate.
+        */
+       csr |= SPI_BF(DLYBS, 0);
+       csr |= SPI_BF(DLYBCT, 0);
 
        /* chipselect must have been muxed as GPIO (e.g. in board setup) */
        npcs_pin = (unsigned int)spi->controller_data;