kgdb: always use icache flush for sw breakpoints

On the ppc 4xx architecture the instruction cache must be flushed as
well as the data cache.  This patch just makes it generic for all
architectures where CACHE_FLUSH_IS_SAFE is set to 1.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/kernel/kgdb.c b/kernel/kgdb.c
index 4d1b3c232377a7c0e07a6c702d5590fbfd873fbb..1bd0ec1c80b284ec06870bc8bc2b2ce726e27815 100644 (file)
--- a/kernel/kgdb.c
+++ b/kernel/kgdb.c
@@ -591,9 +591,9 @@ static void kgdb_flush_swbreak_addr(unsigned long addr)
        if (current->mm && current->mm->mmap_cache) {
                flush_cache_range(current->mm->mmap_cache,
                                  addr, addr + BREAK_INSTR_SIZE);
-       } else {
-               flush_icache_range(addr, addr + BREAK_INSTR_SIZE);
        }
+       /* Force flush instruction cache if it was outside the mm */
+       flush_icache_range(addr, addr + BREAK_INSTR_SIZE);
 }
 
 /*