WARN_ON(div == 0);
clks = omap2_get_clksel_by_parent(clk, clk->parent);
- if (clks == NULL)
+ if (!clks)
- return 0;
+ return ~0;
for (clkr = clks->rates; clkr->div; clkr++) {
if ((clkr->flags & cpu_mask) && (clkr->div == div))
return -EINVAL;
if (clk->usecount > 0)
- _omap2_clk_disable(clk);
+ omap2_clk_disable(clk);
/* Set new source value (previous dividers if any in effect) */
- reg_val = __raw_readl(src_addr) & ~field_mask;
- reg_val |= (field_val << __ffs(field_mask));
- __raw_writel(reg_val, src_addr);
- wmb();
-
- if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
- __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
- wmb();
- }
+ v = _omap2_clk_read_reg(clk->clksel_reg, clk);
+ v &= ~clk->clksel_mask;
+ v |= field_val << __ffs(clk->clksel_mask);
+ _omap2_clk_write_reg(v, clk->clksel_reg, clk);
+ v = _omap2_clk_read_reg(clk->clksel_reg, clk); /* OCP barrier */
+
+ _omap2xxx_clk_commit(clk);
- if (clk->usecount > 0)
- _omap2_clk_enable(clk);
-
clk->parent = new_parent;
+ if (clk->usecount > 0)
+ omap2_clk_enable(clk);
+
/* CLKSEL clocks follow their parents' rates, divided by a divisor */
clk->rate = new_parent->rate;