]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
i386: fix PGE mask
authorBrian Gerst <bgerst@didntduck.org>
Mon, 21 May 2007 12:31:53 +0000 (14:31 +0200)
committerLinus Torvalds <torvalds@woody.linux-foundation.org>
Mon, 21 May 2007 16:56:57 +0000 (09:56 -0700)
cr4 is a 32-bit register, so casting the mask to an unsigned char is wrong,
as it clears more than the PGE bit.

Signed-off-by: Brian Gerst <bgerst@didntduck.org>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
arch/i386/kernel/cpu/mtrr/cyrix.c
arch/i386/kernel/cpu/mtrr/state.c

index 0737a596db434d7e6f9274c7447e3b8daf81e07c..9edf5625584fc6d46bccf11d60941fb10d377446 100644 (file)
@@ -136,7 +136,7 @@ static void prepare_set(void)
        /*  Save value of CR4 and clear Page Global Enable (bit 7)  */
        if ( cpu_has_pge ) {
                cr4 = read_cr4();
-               write_cr4(cr4 & (unsigned char) ~(1 << 7));
+               write_cr4(cr4 & ~X86_CR4_PGE);
        }
 
        /*  Disable and flush caches. Note that wbinvd flushes the TLBs as
index f62ecd15811a9adae409c24c15a2892690e977cd..7b39a2f954d9026c422862d522b5114ead35c242 100644 (file)
@@ -19,7 +19,7 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
                /*  Save value of CR4 and clear Page Global Enable (bit 7)  */
                if ( cpu_has_pge ) {
                        ctxt->cr4val = read_cr4();
-                       write_cr4(ctxt->cr4val & (unsigned char) ~(1 << 7));
+                       write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
                }
 
                /*  Disable and flush caches. Note that wbinvd flushes the TLBs as