[MIPS] tlbex: Cleanup handling of R2 hazards in TLB handlers.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index a61246d3533dd6695ddcbef329cf40ab27800882..511107f92d9c892204d8e0fcc059db16010868db 100644 (file)
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -860,6 +860,12 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
        case tlb_indexed: tlbw = i_tlbwi; break;
        }
 
+       if (cpu_has_mips_r2) {
+               i_ehb(p);
+               tlbw(p);
+               return;
+       }
+
        switch (current_cpu_type()) {
        case CPU_R4000PC:
        case CPU_R4000SC:
@@ -935,14 +941,6 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
                tlbw(p);
                break;
 
-       case CPU_4KEC:
-       case CPU_24K:
-       case CPU_34K:
-       case CPU_74K:
-               i_ehb(p);
-               tlbw(p);
-               break;
-
        case CPU_RM9000:
                /*
                 * When the JTLB is updated by tlbwi or tlbwr, a subsequent