[ARM] 3894/1: pxa27x: Update DCSR_EORINTR bit definition in DCSR

This patch updates a bit definition name to align with the PXA27x
spec.EORINTR(End-Of-Receive Intr) bit in DCSR register (DMA Channel
Control/Status Register)

Signed-off-by: Stanley Cai <stanley.w.cai@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 9b82531e4b5a077f186fd423ab654c89608c7f81..083e03c5639ff4a9c1dfd68364bb5144a7a4df11 100644 (file)
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -99,7 +99,7 @@
 #define DCSR_SETCMPST  (1 << 25)       /* Set Descriptor Compare Status */
 #define DCSR_CLRCMPST  (1 << 24)       /* Clear Descriptor Compare Status */
 #define DCSR_CMPST     (1 << 10)       /* The Descriptor Compare Status */
-#define DCSR_ENRINTR   (1 << 9)        /* The end of Receive */
+#define DCSR_EORINTR   (1 << 9)        /* The end of Receive */
 #endif
 #define DCSR_REQPEND   (1 << 8)        /* Request Pending (read-only) */
 #define DCSR_STOPSTATE (1 << 3)        /* Stop State (read-only) */