_omap2_clk_disable(clk);
}
#endif
+
+int omap2_clk_register(struct clk *clk)
+{
+ omap2_init_clk_clkdm(clk);
+ return 0;
+}
#define OMAP3XXX_EN_DPLL_LOCKED 0x7
int omap2_clk_init(void);
+int omap2_clk_register(struct clk *clk);
int omap2_clk_enable(struct clk *clk);
void omap2_clk_disable(struct clk *clk);
long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
#endif
static struct clk_functions omap2_clk_functions = {
+ .clk_register = omap2_clk_register,
.clk_enable = omap2_clk_enable,
.clk_disable = omap2_clk_disable,
.clk_round_rate = omap2_clk_round_rate,
if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
clk_register(*clkp);
- omap2_init_clk_clkdm(*clkp);
continue;
}
if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
clk_register(*clkp);
- omap2_init_clk_clkdm(*clkp);
continue;
}
}
#if defined(CONFIG_ARCH_OMAP3)
static struct clk_functions omap2_clk_functions = {
+ .clk_register = omap2_clk_register,
.clk_enable = omap2_clk_enable,
.clk_disable = omap2_clk_disable,
.clk_round_rate = omap2_clk_round_rate,
for (clkp = onchip_34xx_clks;
clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
clkp++) {
- if ((*clkp)->flags & cpu_clkflg) {
+ if ((*clkp)->flags & cpu_clkflg)
clk_register(*clkp);
- omap2_init_clk_clkdm(*clkp);
- }
}
/* REVISIT: Not yet ready for OMAP3 */
int clk_register(struct clk *clk)
{
+ int ret;
+
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
mutex_lock(&clocks_mutex);
+ if (arch_clock->clk_register) {
+ ret = arch_clock->clk_register(clk);
+ if (ret)
+ goto cr_out;
+ }
list_add(&clk->node, &clocks);
if (!clk->children.next)
INIT_LIST_HEAD(&clk->children);
omap_clk_add_child(clk->parent, clk);
if (clk->init)
clk->init(clk);
+ ret = 0;
+cr_out:
mutex_unlock(&clocks_mutex);
- return 0;
+ return ret;
}
EXPORT_SYMBOL(clk_register);
struct cpufreq_frequency_table;
struct clk_functions {
+ int (*clk_register)(struct clk *clk);
int (*clk_enable)(struct clk *clk);
void (*clk_disable)(struct clk *clk);
long (*clk_round_rate)(struct clk *clk, unsigned long rate);