return ret;
}
data->next_dmach = data->dma_channel_number1;
- omap_writew(data->dma_channel_number2,
- OMAP_DMA_CLNK_CTRL(data->dma_channel_number1));
- omap_writew(data->dma_channel_number1,
- OMAP_DMA_CLNK_CTRL(data->dma_channel_number2));
+ OMAP_DMA_CLNK_CTRL_REG(data->dma_channel_number1) =
+ data->dma_channel_number2;
+ OMAP_DMA_CLNK_CTRL_REG(data->dma_channel_number2) =
+ data->dma_channel_number1;
return 0;
}
while (cam->free_dmach < 2)
{
- if ((omap_readw(OMAP_DMA_CCR(lch)) & (1 << 7) ))
+ if (OMAP_DMA_CCR_REG(lch) & (1 << 7))
break;
count = (lch == cam->dma_channel_number2) ? 1 : 0;
sg_dma_len(sglist)/(4 * FIFO_TRIGGER_LVL),
OMAP_DMA_SYNC_FRAME,
0, 0);
-
- omap_writew(omap_readw(OMAP_DMA_CLNK_CTRL(dmach)) & ~(1<<15),
- OMAP_DMA_CLNK_CTRL(dmach));
+ OMAP_DMA_CLNK_CTRL_REG(dmach) &= ~( 1<< 15);
prev_dmach = (dmach == data->dma_channel_number2) ?
data->dma_channel_number1 : data->dma_channel_number2;
data->new = 0;
omap16xx_cam_waitfor_syncedge(data, EN_V_UP);
} else {
- if (omap_readw(OMAP_DMA_CCR(prev_dmach)) & (1 << 7)) {
- omap_writew((omap_readw(OMAP_DMA_CLNK_CTRL(prev_dmach)) |
- (1 << 15)),
- OMAP_DMA_CLNK_CTRL(prev_dmach));
- }
+ if (OMAP_DMA_CCR_REG(prev_dmach) & (1 << 7))
+ OMAP_DMA_CLNK_CTRL_REG(prev_dmach) |= (1 << 15);
else {
/* no transfer is in progress */
omap_start_dma(dmach);
skb_reserve(skb, 1);
- w = omap_readw(OMAP_DMA_CDAC(si->rx_dma_channel));
- w -= omap_readw(OMAP_DMA_CDSA_L(si->rx_dma_channel));
+ w = OMAP_DMA_CDAC_REG(si->rx_dma_channel);
+ w -= OMAP_DMA_CDSA_L_REG(si->rx_dma_channel);
if (si->speed != 4000000) {
memcpy(skb_put(skb, w - 2), si->rx_buf_dma_virt, w - 2); /* Copy DMA buffer to skb */
/* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
* read before the DMA controller finished disabling the channel.
*/
- csac = omap_readw(OMAP_DMA_CSAC(lch));
+ csac = OMAP_DMA_CSAC_REG(lch);
if (csac == 0)
- csac = omap_readw(OMAP_DMA_CSAC(lch));
+ csac = OMAP_DMA_CSAC_REG(lch);
return csac;
}
/* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
* read before the DMA controller finished disabling the channel.
*/
- cdac = omap_readw(OMAP_DMA_CDAC(lch));
+ cdac = OMAP_DMA_CDAC_REG(lch);
if (cdac == 0)
- cdac = omap_readw(OMAP_DMA_CDAC(lch));
+ cdac = OMAP_DMA_CDAC_REG(lch);
return cdac;
}
}
#define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
- ? omap_readw(OMAP_DMA_CSAC(x)) /* really: CPC */ \
+ ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
: dma_cdac(x))
static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
/* channel type P: hw synch (fifo) */
if (!cpu_is_omap15xx())
- omap_writew(2, OMAP_DMA_LCH_CTRL(ep->lch));
+ OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
}
just_restart:
else
req = NULL;
- active = ((1 << 7) & omap_readl(OMAP_DMA_CCR(ep->lch))) != 0;
+ active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
active ? "active" : "idle",
sound_curr_lch, ch_status, dma_status, data);
if (dma_status & (DCSR_ERROR)) {
- omap_writew(omap_readw(OMAP_DMA_CCR(sound_curr_lch)) &
- ~DCCR_EN, OMAP_DMA_CCR(sound_curr_lch));
+ OMAP_DMA_CCR_REG(sound_curr_lch) &= ~DCCR_EN;
ERR("DCSR_ERROR!\n");
FN_OUT(-1);
return;
ch_status, dma_status, data);
if (dma_status & (DCSR_ERROR)) {
- omap_writew(omap_readw(OMAP_DMA_CCR(sound_curr_lch)) & ~DCCR_EN,
- OMAP_DMA_CCR(sound_curr_lch));
+ OMAP_DMA_CCR_REG(sound_curr_lch) &= ~DCCR_EN;
ERR("DCSR_ERROR!\n");
FN_OUT(-1);
return;