c->activeQueueHead = NULL;
c->activeQueueTail = NULL;
c->lastHwBDProcessed = NULL;
- c->Channel.bStatus = MGC_DMA_STATUS_UNKNOWN;
+ c->Channel.status = MGC_DMA_STATUS_UNKNOWN;
c->pController = cppi;
c->bLastModeRndis = 0;
c->Channel.private_data = c;
struct cppi_descriptor *bd;
(void) cppi_channel_abort(&c->Channel);
- c->Channel.bStatus = MGC_DMA_STATUS_UNKNOWN;
+ c->Channel.status = MGC_DMA_STATUS_UNKNOWN;
c->pController = NULL;
/* free all its bds */
DBG(1, "re-allocating DMA%d %cX channel %p\n",
chNum, bTransmit ? 'T' : 'R', otgCh);
otgCh->hw_ep = ep;
- otgCh->Channel.bStatus = MGC_DMA_STATUS_FREE;
+ otgCh->Channel.status = MGC_DMA_STATUS_FREE;
DBG(4, "Allocate CPPI%d %cX\n", chNum, bTransmit ? 'T' : 'R');
otgCh->Channel.private_data = otgCh;
/* for now, leave its cppi IRQ enabled (we won't trigger it) */
c->hw_ep = NULL;
- channel->bStatus = MGC_DMA_STATUS_UNKNOWN;
+ channel->status = MGC_DMA_STATUS_UNKNOWN;
}
/* Context: controller irqlocked */
struct cppi *pController = otgChannel->pController;
struct musb *musb = pController->musb;
- switch (pChannel->bStatus) {
+ switch (pChannel->status) {
case MGC_DMA_STATUS_BUS_ABORT:
case MGC_DMA_STATUS_CORE_ABORT:
/* fault irq handler should have handled cleanup */
break;
}
- pChannel->bStatus = MGC_DMA_STATUS_BUSY;
+ pChannel->status = MGC_DMA_STATUS_BUSY;
/* set transfer parameters, then queue up its first segment */
otgChannel->startAddr = dma_addr;
>= txChannel->transferSize) {
txChannel->activeQueueHead = NULL;
txChannel->activeQueueTail = NULL;
- txChannel->Channel.bStatus =
+ txChannel->Channel.status =
MGC_DMA_STATUS_FREE;
hw_ep = txChannel->hw_ep;
}
/* all segments completed! */
- rxChannel->Channel.bStatus = MGC_DMA_STATUS_FREE;
+ rxChannel->Channel.status = MGC_DMA_STATUS_FREE;
hw_ep = rxChannel->hw_ep;
pController = otgCh->pController;
chNum = otgCh->chNo;
- switch (channel->bStatus) {
+ switch (channel->status) {
case MGC_DMA_STATUS_BUS_ABORT:
case MGC_DMA_STATUS_CORE_ABORT:
/* from RX or TX fault irq handler */
* refers to an entire "DMA packet" not just emptying the
* current fifo; most segments need multiple usb packets.
*/
- if (channel->bStatus == MGC_DMA_STATUS_BUSY)
+ if (channel->status == MGC_DMA_STATUS_BUSY)
udelay(50);
/* scan the current list, reporting any data that was
}
}
- channel->bStatus = MGC_DMA_STATUS_FREE;
+ channel->status = MGC_DMA_STATUS_FREE;
otgCh->startAddr = 0;
otgCh->currOffset = 0;
otgCh->transferSize = 0;
* @wMaxLength: the maximum number of bytes the channel can move in one
* transaction (typically representing many USB maximum-sized packets)
* @actual_len: how many bytes have been transferred
- * @bStatus: current channel status (updated e.g. on interrupt)
+ * @status: current channel status (updated e.g. on interrupt)
* @bDesiredMode: TRUE if mode 1 is desired; FALSE if mode 0 is desired
*
* channels are associated with an endpoint for the duration of at least
// FIXME not void* private_data, but a dma_controller *
size_t max_len;
size_t actual_len;
- enum dma_channel_status bStatus;
+ enum dma_channel_status status;
u8 bDesiredMode;
};
static inline enum dma_channel_status
dma_channel_status(struct dma_channel *c)
{
- return (is_dma_capable() && c) ? c->bStatus : MGC_DMA_STATUS_UNKNOWN;
+ return (is_dma_capable() && c) ? c->status : MGC_DMA_STATUS_UNKNOWN;
}
/**
wCsrVal &= ~MGC_M_TXCSR_P_SENTSTALL;
musb_writew(epio, MGC_O_HDRC_TXCSR, wCsrVal);
if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
- dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
+ dma->status = MGC_DMA_STATUS_CORE_ABORT;
musb->dma_controller->channel_abort(dma);
}
if (wCsrVal & MGC_M_RXCSR_P_SENTSTALL) {
if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
- dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
+ dma->status = MGC_DMA_STATUS_CORE_ABORT;
(void) musb->dma_controller->channel_abort(dma);
pRequest->actual += musb_ep->dma->actual_len;
}
if (status) {
if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
- dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
+ dma->status = MGC_DMA_STATUS_CORE_ABORT;
(void) musb->dma_controller->channel_abort(dma);
}
if (status) {
/* clean up dma and collect transfer count */
if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
- dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
+ dma->status = MGC_DMA_STATUS_CORE_ABORT;
(void) musb->dma_controller->channel_abort(dma);
xfer_len = dma->actual_len;
}
* shouldn't this be the "half full" double buffer case?
*/
if (dma_channel_status(dma) == MGC_DMA_STATUS_BUSY) {
- dma->bStatus = MGC_DMA_STATUS_CORE_ABORT;
+ dma->status = MGC_DMA_STATUS_CORE_ABORT;
(void) musb->dma_controller->channel_abort(dma);
xfer_len = dma->actual_len;
bDone = TRUE;
pImplChannel->bTransmit = bTransmit;
pChannel = &(pImplChannel->Channel);
pChannel->private_data = pImplChannel;
- pChannel->bStatus = MGC_DMA_STATUS_FREE;
+ pChannel->status = MGC_DMA_STATUS_FREE;
pChannel->max_len = 0x10000;
/* Tx => mode 1; Rx => mode 0 */
pChannel->bDesiredMode = bTransmit;
pImplChannel->pController->bmUsedChannels &=
~(1 << pImplChannel->bIndex);
- pChannel->bStatus = MGC_DMA_STATUS_UNKNOWN;
+ pChannel->status = MGC_DMA_STATUS_UNKNOWN;
}
static void configure_channel(struct dma_channel *pChannel,
pImplChannel->bTransmit ? "Tx" : "Rx",
wPacketSize, dma_addr, dwLength, bMode);
- BUG_ON(pChannel->bStatus == MGC_DMA_STATUS_UNKNOWN ||
- pChannel->bStatus == MGC_DMA_STATUS_BUSY);
+ BUG_ON(pChannel->status == MGC_DMA_STATUS_UNKNOWN ||
+ pChannel->status == MGC_DMA_STATUS_BUSY);
pChannel->actual_len = 0;
pImplChannel->dwStartAddress = dma_addr;
pImplChannel->len = dwLength;
pImplChannel->wMaxPacketSize = wPacketSize;
- pChannel->bStatus = MGC_DMA_STATUS_BUSY;
+ pChannel->status = MGC_DMA_STATUS_BUSY;
if ((bMode == 1) && (dwLength >= wPacketSize)) {
configure_channel(pChannel, wPacketSize, 1, dma_addr,
u8 *mbase = pImplChannel->pController->pCoreBase;
u16 csr;
- if (pChannel->bStatus == MGC_DMA_STATUS_BUSY) {
+ if (pChannel->status == MGC_DMA_STATUS_BUSY) {
if (pImplChannel->bTransmit) {
csr = musb_readw(mbase,
musb_writel(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_COUNT), 0);
- pChannel->bStatus = MGC_DMA_STATUS_FREE;
+ pChannel->status = MGC_DMA_STATUS_FREE;
}
return 0;
}
MGC_O_HSDMA_CONTROL));
if (wCsr & (1 << MGC_S_HSDMA_BUSERROR)) {
- pImplChannel->Channel.bStatus =
+ pImplChannel->Channel.status =
MGC_DMA_STATUS_BUS_ABORT;
} else {
dwAddress = musb_readl(mbase,
u8 devctl = musb_readb(mbase,
MGC_O_HDRC_DEVCTL);
- pChannel->bStatus = MGC_DMA_STATUS_FREE;
+ pChannel->status = MGC_DMA_STATUS_FREE;
/* completed */
if ((devctl & MGC_M_DEVCTL_HM)
if (!dmareq_works())
tusb_omap_free_shared_dmareq(chdat);
- channel->bStatus = MGC_DMA_STATUS_FREE;
+ channel->status = MGC_DMA_STATUS_FREE;
/* Handle only RX callbacks here. TX callbacks musb be handled based
* on the TUSB DMA status interrupt.
chdat->len = len;
channel->actual_len = 0;
chdat->dma_addr = (void __iomem *)dma_addr;
- channel->bStatus = MGC_DMA_STATUS_BUSY;
+ channel->status = MGC_DMA_STATUS_BUSY;
/* Since we're recycling dma areas, we need to clean or invalidate */
if (chdat->tx) {
tusb_dma->sync_dev = -1;
}
- channel->bStatus = MGC_DMA_STATUS_FREE;
+ channel->status = MGC_DMA_STATUS_FREE;
return 0;
}
for (i = 0; i < MAX_DMAREQ; i++) {
struct dma_channel *ch = dma_channel_pool[i];
- if (ch->bStatus == MGC_DMA_STATUS_UNKNOWN) {
- ch->bStatus = MGC_DMA_STATUS_FREE;
+ if (ch->status == MGC_DMA_STATUS_UNKNOWN) {
+ ch->status = MGC_DMA_STATUS_FREE;
channel = ch;
chdat = ch->private_data;
break;
tusb_omap_dma_free_dmareq(chdat);
DBG(3, "ep%i: Could not get a DMA channel\n", chdat->epnum);
- channel->bStatus = MGC_DMA_STATUS_UNKNOWN;
+ channel->status = MGC_DMA_STATUS_UNKNOWN;
return NULL;
}
reg |= (1 << (chdat->epnum + 15));
musb_writel(tusb_base, TUSB_DMA_INT_CLEAR, reg);
- channel->bStatus = MGC_DMA_STATUS_UNKNOWN;
+ channel->status = MGC_DMA_STATUS_UNKNOWN;
if (chdat->ch >= 0) {
omap_stop_dma(chdat->ch);
if (!chdat)
goto cleanup;
- ch->bStatus = MGC_DMA_STATUS_UNKNOWN;
+ ch->status = MGC_DMA_STATUS_UNKNOWN;
ch->private_data = chdat;
}