MMC: CSD and CID timeout values

The MMC spec states that the timeout for accessing the CSD and CID
registers is 64 clock cycles.

Signed-off-by: Matthew Fleming <matthew.fleming@imgtec.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>

diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c
index 64b05c6270f2f3aef54d88e309f8772694c4347a..9c50e6f1c23649d75ba0a2522f5e52b04ff4740e 100644 (file)
--- a/drivers/mmc/core/mmc_ops.c
+++ b/drivers/mmc/core/mmc_ops.c
@@ -248,8 +248,12 @@ mmc_send_cxd_data(struct mmc_card *card, struct mmc_host *host,
 
        sg_init_one(&sg, data_buf, len);
 
-       if (card)
-               mmc_set_data_timeout(&data, card);
+       /*
+        * The spec states that CSR and CID accesses have a timeout
+        * of 64 clock cycles.
+        */
+       data.timeout_ns = 0;
+       data.timeout_clks = 64;
 
        mmc_wait_for_req(host, &mrq);