static void omap2_enter_full_retention(void)
{
- u32 sleep_time = 0;
+ u32 l, sleep_time = 0;
/* There is 1 reference hold for all children of the oscillator
* clock, the following will remove it. If no one else uses the
clk_enable(osc_ck);
+ /* clear CORE wake-up events */
+ prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+ prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+
+ /* wakeup domain events */
+ l = prm_read_mod_reg(WKUP_MOD, PM_WKST);
+ l &= 0x5; /* bit 1: GPT1, bit5 GPIO */
+ prm_write_mod_reg(l, WKUP_MOD, PM_WKST);
+
+ /* MPU domain wake events */
+ l = prm_read_reg(OMAP24XX_PRCM_IRQSTATUS_MPU);
+ if (l & 0x01)
+ prm_write_reg(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU);
+ if (l & 0x20)
+ prm_write_reg(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU);
+
+ /* Mask future PRCM-to-MPU interrupts */
+ prm_write_reg(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU);
}
static int omap2_i2c_active(void)
prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP);
prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
+ prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
+ if (cpu_is_omap2430())
+ prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
/* Enable retention for all memory blocks */